Dynamic On-state Resistance Research Articles

Dynamic On-State Resistance and Threshold-Voltage Instability in SiC MOSFETs

Dynamic on-state resistance has been experimentally observed in all commercially-available SiC MOSFETs studied on the time scale of normal device operation, and can be explained by the presence of dynamic threshold-voltage instability. The magnitude of this dynamic on-state resistance varies from vendor to vendor, but in every case this magnitude generally corresponds to the magnitude of that device’s threshold-voltage instability, as described by standard textbook equations-especially in the case of large threshold-voltage instabilities.

A Flexible Setup for Dynamic On-State Resistance Measurements of GaN HEMTs With One-Factor-at-a-Time Capability

A Flexible Setup for Dynamic On-State Resistance Measurements of GaN HEMTs With One-Factor-at-a-Time Capability

Alleviation of the on-state dynamic conductance decline in a GaN high electron mobility transistor with heavy carbon doping

Carbon doping is a standard blocking-voltage-enhancing technique for commercial silicon substrate-based AlGaN/GaN power switching transistors, although the incorporation of carbon into GaN may deteriorate the dynamic on-state resistance (dy-R on) properties of the device. Commonly, researchers have believed that the greater the carbon doping, the greater the deterioration in dy-R on. Surprisingly, in this work, the opposite was observed: the dy-R on value decreased as the carbon concentration increased, particularly when the density exceeded several 1017 cm−3. This phenomenon is explained by the effect of electric field-induced band-to-band electron tunneling into the two-dimensional electron gas (2DEG) conduction channel, originating from the ionization of acceptor-like nitrogen site carbon atoms (CN) in the device off-state with large drain bias. Simulation data indicated that negatively ionized CN may generate a much larger electric field in samples with higher carbon doping, which may induce a narrower 2DEG back energy band barrier that increases the possibility of electron band-to-band tunneling.

Physics-Based SPICE Modeling of Dynamic on-State Resistance of p-GaN HEMTs

This letter introduces a new physics based SPICE modeling method for the dynamic on-state resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,dy</sub> ) of gallium nitride based p-type gate power high electron mobility transistors (p-GaN HEMTs). To describe the continuous variations of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,dy</sub> , a time-resolved electron mobility variation (Δ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) model is proposed. Physical parameters including activation energy and voltage acceleration factor of traps in p-GaN HEMTs are extracted as the model parameters. Then, to achieve the goal of simulating Ron,dy, the proposed Δμeff model is incorporated into the surface potential based advanced SPICE model for GaN HEMT (ASM-HEMT). Simulative results prove the proposed models can predict the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,dy</sub> induced power loss.

Paralleled multi-GaN MIS–HEMTs integrated cascode switch for power electronic applications

A cascode gallium nitride (GaN) switch integrating four paralleled GaN depletion-mode metal–insulator–semiconductor–high-electron-mobility transistors (MIS–HEMT) and a silicon MOSFET (Si-MOSFET) is presented. Each GaN chip is wire-bonded into a multi-chip power module to scale up the power rating. An optimized symmetric configuration and wire bonding of an integral package are used in the cascode switch. By utilizing an optimized packaging approach, the performance of the multi-GaN-chip cascode switch was evaluated through both static and dynamic characterizations. The constructed cascode switch provides a low-static on-state resistance of 72 mΩ and an off-state blocking capability of 400 V with a positive threshold voltage of 2 V. Analysis of dynamic switching characteristics are discussed and demonstrates stable dynamic on-state resistance (R DS-ON) in inductive load circuits with switching dependencies of voltage, frequency, time, and temperature. The extended defects from buffer caused a minimal decrease in dynamic and static R DS-ON with respect to hard switching conditions. However, there was no noticeable degradation in R DS-ON under harsh switching conditions. This study provides a complete analysis of the multi-GaN-chip cascode switch, including MIS–HEMT manufacturing, cascode packaging and static and dynamic characterizations.

Comparisons and Evaluations of Silicon and Wide Band Gap Devices at Cryogenic Temperature

In this article, the static and dynamic characterizations for semiconductors with different materials, including silicon (Si), silicon carbide (SiC), and gallium nitride (GaN), are evaluated and compared at room temperature and cryogenic temperature (liquid nitrogen temperature). For static characterizations, the on-state resistance and threshold voltage are evaluated. For dynamic characterizations, the turn-on switching loss, turn-off switching loss, and dynamic on-state resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds(on)</sub> ) are evaluated. The results demonstrate that Si and GaN based semiconductors have improved performances with lower on-state resistance and faster switching speed at low temperature operations. For SiC based semiconductors, the on-state resistance increases significantly at cryogenic temperature. The switching speed is reduced dramatically for the evaluated 1.2 kV SiC metal oxide semiconductor field effect transistors (MOSFETs) at cryogenic temperature. This makes it less attractive for cryogenic applications. For the evaluated 650 V and 900 V SiC MOSFETs, the switching speed remains almost unchanged at low temperature. GaN high electron mobility transistor (HEMT) demonstrates a fast turn-on switching speed at low temperature, where the device's <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">di/dt</i> are almost doubled when compared with room temperature. In addition, the dynamic <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds(on)</sub> of the evaluated GaN HEMTs also decreases at low temperatures. The evaluation results can serve as guidelines for cryogenic power electronics applications. Meanwhile, the future work for semiconductors cryogenic characterizations is discussed.

Effect of Dynamic Threshold-Voltage Instability on Dynamic ON-State Resistance in SiC MOSFETs

This work presents an investigation of several important phenomena related to threshold-voltage instability in SiC MOSFETs. Such instability can occur in previously unstressed as-processed devices, including trench-geometry devices, when exposed to a negative gate-bias overstress. This work also reports, for the first time for SiC MOSFETs, on the dynamic nature of ON resistance in the presence of large threshold-voltage instabilities, whether occurring in as-processed devices or due to an ac stress-induced degradation.

Review of Pulse Test Setup for the Switching Characterization of GaN Power Devices

Pulse test techniques are widely adopted in characterizing both the static and dynamic performances of semiconductor devices considering various device structures and operating conditions. For gallium nitride (GaN) devices, due to the current collapse phenomenon, fast and accurate measurement of their key electrical parameters, such as dynamic ON-state resistance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {ds}, \mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> , switching rising time, fall time, switching losses, and short-circuit (SC) robustness, becomes essential. This article presents a comprehensive review of state-of-the-art pulse test setup methods such as the double-pulse test (DPT), multiple-pulse test (MPT), and SC test (SCT) for the first time, which facilitates the GaN device structure design and practical applications in high efficiency and power density power converters.

Development of a Device for On-Die Double-Pulse Testing and Measurement of Dynamic On-Resistance of GaN HEMTs

On-die testing can accelerate development of semiconductor devices, but poses certain challenges related to high frequency and high current switching. This paper describes design and development of a tester for double-pulse switching test and measurement of dynamic on-state resistance of unpackaged High-Electron-Mobility Transistors (GaN HEMTs). The tester is capable of switching an inductive load at drain-to-source voltage up to 400 V and drain current up to 10 A. Design challenges resulting from specific properties of GaN HEMTs and on-die measurement are explained, and solutions are proposed. Essential parts of the developed device are described, including low inductance gate-driver and measurement methods. Modified drain voltage clamping circuit for accurate on-state drain voltage measurement is described. The tester is constructed as a printed circuit board, integrated into a probe station. Voltage and current waveforms are measured with oscilloscope and used to calculate the on-resistance. Results of a reference measurement with commercially available packaged transistors are presented. Waveforms measured on experimental unpackaged normally-off GaN HEMT samples are also presented and discussed. The proposed tester device proved to be capable of performing the dynamic on-resistance measurement with satisfactory results.

A Novel Approach for the Modeling of the Dynamic ON-State Resistance of GaN-HEMTs

A compact model approach to enhance the accuracy and facilitate the parameter extraction of trapping models is presented. The proposed model replaces the conventional superposition of discrete trapping time constants by a Gaussian distribution of a particular range of time constants. This approach reflects the physically non-constant energy levels of the trap distribution of surface, interface, and bulk traps. Also, we propose a new equivalent circuit that takes the time-dependent charging and discharging of traps into account. We show that our model reduces the model complexity by 52%. The model is verified against dynamic ON-state resistance ( R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS,ON</sub> ) measurements of a commercial 100-V gallium-nitride (GaN) power transistor in soft-switching operation.

Mechanism Analysis of Dynamic On-State Resistance Degradation for a Commercial GaN HEMT Using Double Pulse Test

The dynamic on-resistance (RON) behavior of one commercial GaN HEMT device with p-GaN gate is investigated under hard-switching conditions. The non-monotonic performance of dynamic RON with off-state voltage ranging from 50 to 400 V is ascribed to the “leaky dielectric” model. The highest normalized RON value of 1.22 appears at 150 and 200 V. The gradual increase and following maximum of dynamic RON are found when the device is exposed to a stress voltage for an extended stress time under 100 and 200 V, which is due to a much longer trapping time compared to detrapping time related to deep acceptors and donors. No obvious RON degradation, thanks to the suppressed trapping effect, is observed at higher VDS. From the multi-pulse test, the dynamic RON is seen to be insensitive to the frequency. It is demonstrated that the leakage, especially under source and drain contact, is a key issue in the dynamic resistance degradation.

Comparison of Wide-Band-Gap Technologies for Soft-Switching Losses at High Frequencies

Soft-switching power converters based on wide-bandgap (WBG) transistors offer superior efficiency and power density advantages. However, at high frequencies, loss behavior varies significantly between different WBG technologies. This includes losses related to conduction and dynamic ON-state resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS(ON)</sub> ) degradation, also charging/discharging of input capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ISS</sub> ) and output capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OSS</sub> ). As datasheets lack such important information, we present measurement techniques and evaluation methods for soft-switching losses in WBG transistors which enable a detailed loss-breakdown analysis. We estimate the gate loss under soft-switching conditions using a simple small-signal measurement. Next, we use Sawyer-Tower and nonlinear resonance (NR) methods to measure large-signal C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OSS</sub> energy losses up to 40 MHz. Finally, we investigate the dependence of dynamic R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS(ON)</sub> degradation on OFF-state voltage using pulsed-IV measurements. We demonstrate an insightful comparison of soft-switching losses for various normally OFF gallium nitride (GaN) and silicon carbide (SiC) devices. A p-GaN-gated device exhibits the most severe RDS(ON) degradation and the lowest gate loss. Cascode arrangement increases threshold voltage for GaN devices and reduces gate losses in SiC transistors; however, it leads to higher C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OSS</sub> losses. The study facilitates the evaluation of system losses and selection of efficient WBG devices based on the trade-offs between various sources of losses at high frequencies.

Quantifying Dynamic On-State Resistance of GaN HEMTs for Power Converter Design via a Survey of Low and High Voltage Devices

Designing and optimizing high switching frequency, ultra-efficient converters requires detailed knowledge of the behavior and parasitic parameters for both active and passive components. Recently, wide bandgap transistors have enabled simultaneous increases in both switching frequency and efficiency due to higher maximum operating junction temperature limits, lower dc on-state resistances, and reduced parasitic inductances and capacitances. Yet, the early acceptance of gallium-nitride (GaN) switches was plagued by detrimental dynamic on-state resistance effects. This complex phenomenon for GaN devices is characterized by deviations in on-state resistance from dc operating characteristics based on design choices such as the magnitude and duration of both voltage and current stress, switching mode, and junction temperature. While device manufacturers have made improvements compared to early generation devices, experimental evidence from a survey of commercial GaN transistors highlight measurable change in on-state resistance still exists due to variations in voltage stress during hard-switching operation. After sharing insights for obtaining low noise measurements, an analysis method along with two metrics are proposed to characterize dynamic on-state resistance measurements for power electronics designers. Quantifying the performance of GaN devices with standardized metrics facilitates a fair comparison between different GaN device technologies during converter development, enables manufacturing qualification for GaN switches, and provides a benchmark to catalyze improvement for the next generation of GaN device development.

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Power Loss Characterization and Modeling for GaN-Based Hard-Switching Half-Bridges Considering Dynamic on-State Resistance

Gallium nitride enhancement-mode high electron mobility transistors (GaN E-HEMTs) can achieve high frequency and high efficiency due to its excellent switching performance compared with conventional Si transistors. Nevertheless, GaN HEMTs exhibit a more pronounced dynamic ON-state resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS(ON)</sub> than silicon transistors. The variation of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS(ON)</sub> is caused by both the static R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS(ON)</sub> due to junction temperature rise and the dynamic RDS(ON) due to the electron trapping. Without a careful decoupling analysis, it is difficult to calculate and model the dynamic R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS(ON)</sub> portion. This article introduces a comprehensive approach of dynamic R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS(ON)</sub> evaluation comprising four techniques: 1) a clamping circuit for both the hard-switching (HS) device and synchronous rectification (SR) device; 2) a junction temperature monitoring technique; 3) control of both the pulse test and soak time; and 4) continuous operation of device under test. Based on the dynamic RDS(ON) test results, a new model of the RDS(ON) variation is developed where two coefficients k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Tj</sub> and k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dR</sub> are defined to model the contribution of the heating effect and the impact of the trapping effect, respectively. The RDS(ON) model is validated by the comparison between the calculated and measured junction temperatures of a 650-V/30-A GaN-based half-bridge. Furthermore, a detailed loss breakdown analysis is conducted for the GaN-based HS half-bridge. The results show that the switching losses, E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> and E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> , are the dominant loss factors with high switching frequency. At last, the possible efficiency improvements are also discussed in detail.

Test Setup for Dynamic ON-State Resistance Measurement of High- and Low-Voltage GaN-HEMTs Under Hard and Soft Switching Operations

GaN-HEMTs impress with excellent properties, and therefore power electronics engineers pay a lot of attention to them. However, during switching operation some devices show increased ON-state resistance. Since, for switch mode power supply designers, the internal device structure is not apparent, measuring the ON-state resistance under the targeted operating conditions is the only method to gain this information. In order to characterize the dynamic ON-state resistance, this article proposes a clamping circuit for accurate measurement. Using a high-resolution digitizer card ensures precise results. The presented measurement setup allows to measure the ON-state resistance under hard and soft switching conditions with parameters of the intended application. In inverter applications, each switch works under hard as well as soft switching. Therefore, the transition between these two operating modes must also be studied in detail. Finally, an extension of the clamping circuit is presented allowing measurements with high-voltage GaN-HEMTs as well. The initial results verify the improved setup.

Physical mechanism on the suppression of dynamic resistance degradation by multi-mesa-channel in AlGaN/GaN high electron mobility transistors

In this letter, the suppression of dynamic on-state resistance (RON) degradation for faster dynamic RON recovery is achieved by the multimesa-channel (MMC) structure in AlGaN/GaN high electron mobility transistors. The measurement results are discussed with the physical mechanisms investigated. The initial transient RON degradation is reduced in the MMC structure, resulting from the lower peak electric field around the drain-side gate edge in the trigate structure compared to that in a planar device. The faster dynamic RON recovery in MMC devices is attributed to the quick emission of electrons at sidewall traps of shallower energy levels. The energy levels of dominant traps at the sidewall and top interfaces are found to be 0.26 eV and 0.37 eV below the conduction band edge, respectively, verified by Technology Computer Aided Design simulations in agreement with the measurement data.

Impact of Gamma Radiation on Dynamic RDSON Characteristics in AlGaN/GaN Power HEMTs.

GaN high-electron-mobility transistors (HEMTs) are promising next-generation devices in the power electronics field which can coexist with silicon semiconductors, mainly in some radiation-intensive environments, such as power space converters, where high frequencies and voltages are also needed. Its wide band gap (WBG), large breakdown electric field, and thermal stability improve actual silicon performances. However, at the moment, GaN HEMT technology suffers from some reliability issues, one of the more relevant of which is the dynamic on-state resistance (RON_dyn) regarding power switching converter applications. In this study, we focused on the drain-to-source on-resistance (RDSON) characteristics under 60Co gamma radiation of two different commercial power GaN HEMT structures. Different bias conditions were applied to both structures during irradiation and some static measurements, such as threshold voltage and leakage currents, were performed. Additionally, dynamic resistance was measured to obtain practical information about device trapping under radiation during switching mode, and how trapping in the device is affected by gamma radiation. The experimental results showed a high dependence on the HEMT structure and the bias condition applied during irradiation. Specifically, a free current collapse structure showed great stability until 3.7 Mrad(Si), unlike the other structure tested, which showed high degradation of the parameters measured. The changes were demonstrated to be due to trapping effects generated or enhanced by gamma radiation. These new results obtained about RON_dyn will help elucidate trap behaviors in switching transistors.

Dynamic on-State Resistance Test and Evaluation of GaN Power Devices Under Hard- and Soft-Switching Conditions by Double and Multiple Pulses

The dynamic on -state resistance ( R DSON) behavior of commercial GaN devices is very important for a GaN-based converter. Since the zero-voltage switching techniques are popular in high-frequency power conversion, a dynamic R DSON test board integrating both hard- and soft-switching test circuits is built in this study. Two types of commercial GaN devices are tested and compared under hard- and soft-switching conditions by double-pulse and multipulse test modes, respectively. It has been found that their dynamic R DSON exhibit different behaviors depending on the off -state voltage and frequency under hard- and soft-switching conditions due to different device technologies, which should be taken fully into account for GaN-based converter design and loss estimation. In order to simulate the R DSON behavior in a steady-state operating converter, a multipulse measurement has been implemented, the results of which are compared with that of double-pulse test. Furthermore, the primary trapping mechanisms responsible for dynamic R DSON increase under different switching conditions are identified and verified by the numerical device simulation using Silvaco TCAD tool.

Characterisation and Modeling of Gallium Nitride Power Semiconductor Devices Dynamic On-State Resistance

Gallium nitride high-electron-mobility transistors (GaN-HEMTs) suffer from trapping effects that increases device on-state resistance ( $R_\mathrm{DS(on)}$ ) above its theoretical value. This increase is a function of the applied dc bias when the device is in its off state, and the time which the device is biased for. Thus, dynamic $R_\mathrm{DS(on)}$ of different commercial GaN-HEMTs are characterised at different bias voltages in the paper by a proposed new measurement circuit. The time-constants associated with trapping and detrapping effects in the device are extracted using the proposed circuit and it is shown that variations in $R_\mathrm{DS(on)}$ can be predicted using a series of RC circuit networks. A new methodology for integrating these $R_\mathrm{DS(on)}$ predictions into existing gallium nitride-high-electron-mobility transistors models in standard SPICE simulators to improve model accuracy is then presented. Finally, device dynamic $R_\mathrm{DS(on)}$ values of the model is compared and validated with the measurement when it switches in a power converter with different duty cycles and switching voltages.