Dynamic Memory Management Research Articles

State Vector Identification of Hybrid Model of a Gas Turbine by Real-Time Kalman Filter

A model and real-time simulation of a gas turbine engine (GTE) by real-time tasks (RTT) is presented. A Kalman filter is applied to perform the state vector identification of the GTE model. The obtained algorithms are recursive and multivariable; for this reason, ANSI C libraries have been developed for (a) use of matrices and vectors, (b) dynamic memory management, (c) simulation of state-space systems, (d) approximation of systems using equations in matrix finite difference, (e) computing the mean square errors vector, and (f) state vector identification of dynamic systems through digital Kalman filter. Simulations were performed in a Single Board Computer (SBC) Raspberry Pi 2® with a real-time operating system. Execution times have been measured to justify the real-time simulation. To validate the results, multiple time plots are analyzed to verify the quality and convergence time of the mean square error obtained.

Hierarchical Behavior Model for Multi-Agent System with Evasion Capabilities and Dynamic Memory

The behavior of an agent may be simple or complex depending on its role. Behavioral simulation using agents can have multiple approaches that have different advantages and disadvantages. By combining different behaviors in a hierarchical model, situational inefficiencies can be compensated. This paper proposes a behavioral hierarchy model that combines different mechanisms in behavior plans. The study simulates the social behavior in an office environment during an emergency using collision avoidance, negotiation, conflict solution, and path-planning mechanisms in the same multi-agent model to find their effects and the efficiency of the combinational setups. Independent agents were designed to have memory expansion, pathfinding, and searching capabilities, and the ability to exchange information among themselves and perform evasive actions to find a way out of congestion and conflict. The designed model allows us to modify the behavioral hierarchy and action order of agents during evacuation scenarios. Moreover, each agent behavior can be enabled or disabled separately. The effects of these capabilities on escape performance were measured in terms of time required for evacuation and evacuation ratio. Test results prove that all mechanisms in the proposed model have characteristics that fit each other well in situations where different hierarchies are needed. Dynamic memory management (DMM), together with a hierarchical behavior plan, achieved a performance improvement of 23.14% in escape time without providing agents with any initial environmental information.

Group system: An efficient dynamic memory management scheme for real-time systems

While dynamic memory management (DMM) has been widely used as one of the basic elements of computer systems, it has been rarely used in real-time systems. DMM in real-time systems must exhibit fast execution, high memory efficiency, and predictable execution time. However, it is difficult to design a DMM scheme that simultaneously satisfies all of these requirements, and therefore DMM has not been widely used in real-time systems. This study proposes a new DMM scheme, named group system, that simultaneously satisfies the three requirements of real-time systems. The new DMM scheme is an extension of buddy systems and provides significantly improved memory efficiency compared to buddy systems while maintaining the advantage of the predictable execution time of buddy systems. Group system shows a slightly better worst-case execution time (WCET) than buddy systems that are known to exhibit excellent execution time, and shows memory efficiency that is close to that of the best fit scheme that is known to have excellent memory efficiency.

MxU

The advanced functionality requirements of modern embedded and Internet of Things (IoT) devices -- from autonomous vehicles, to city and power-grid management -- are driving an ever-increasing software complexity. At the same time, the pervasive internet connections of these systems necessitate the fundamental design of security into these devices. The isolation of complex features from those that are critical through protection domains is an effective means to constrain the scope of faults and security breaches. Common hardware-provided memory facilities to enforce protection domains through memory access control -- including Memory Management Units (MMUs) usually found in microprocessors, and Memory Protection Units (MPUs) usually found in microcontrollers -- must meet the goals of enabling flexible, efficient and dynamic management of memory , and must enable tight bounds on the worst-case execution of critical code. Unfortunately, current system memory management facilities are ill-prepared to handle this challenge: MMUs that use extensive caches to achieve strong average-case performance suffer from debilitating worst-case and even average-case behavior under hefty interference, while MPUs struggle to provide flexible memory management. This paper details MxU, a memory protection and allocation abstraction that integrates temporal specifications into the memory management subsystem, to enable portable code to achieve both predictable, tightly-bounded execution and dynamic management across both MMU- and MPU-based systems. We implement MxU in the Composite microkernel, and evaluate its flexibility and predictability over two different architectures: a MPU-based Cortex-M7 microcontroller and a MMU-based Cortex-A9 microprocessor using a suite of modern applications including neural network-based inference, SQLite, and a javascript runtime. For MMU-based systems, MxU reduces application TLB stall by up to 68.0%. For MPU-based systems, MxU enables flexible dynamic memory management often with application overheads of 1%, increasing to 6.1% under significant interference.

Hardware Dynamic Memory Manager for Hard Real-Time Systems

This paper presents novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations that are suitable for hard real-time and safety-critical systems due to very high determinism of these operations. The proposed memory manager implements Worst-Fit algorithm for selection of suitable free block of memory that can be used by the external environment, e.g. CPU. The deterministic timing of the memory allocation and deallocation operations is essential for hard real-time systems. The proposed memory manager performs these operations in nearly constant time thanks to the adoption of hardware-accelerated max queue, which is a data structure that continuously provides the largest free block of memory in two clock cycles regardless of actual number or constellation of existing free blocks of memory. In order to minimize the overhead caused by implementing the memory management in hardware, the max queue was optimized by developing a new sorting architecture, called Rocket-Queue. The Rocket-Queue architecture as well as the whole memory manager is described in this paper in detail. The memory manager and the Rocket-Queue architecture were verified using simplified version of UVM and applying billions of randomly generated instructions as testing inputs. The Rocket-Queue architecture was synthesized into Intel FPGA Cyclone V with 100 MHz clock frequency and the results show that it consumes from 17,06% to 38,67% less LUTs than the existing architecture, called Systolic Array. The memory manager implemented in a form of a coprocessor that provides four custom instructions was synthesized into 28nm TSMC HPM technology with 1 GHz clock frequency and 0.9V power supply. The ASIC synthesis results show that the Rocket-Queue based memory manager can occupy up to 24,59% smaller chip area than the Systolic Array based manager. In terms of total power consumption, the Rocket-Queue based memory manager consumes from 15,16% to 42,95% less power.

Low-overhead dynamic sharing of graphics memory space in GPU virtualization environments

The proliferation of GPU intensive workloads has created a new challenge for low-overhead and efficient GPU virtualization solutions over GPU clouds. gVirt is a full GPU virtualization solution for Intel’s integrated GPUs that share system’s on-board memory for graphics memory. In order to solve the inherent scalability limitation on the number of simultaneous virtual machines (VM) in gVirt, gScale proposed a dynamic sharing scheme for global graphics memory among VMs by copying the entries in a private graphics translation table (GTT) to a physical GTT along with a GPU context switch. However, copying entries between private GTT and physical GTT often causes significant overhead, which becomes worse when the global graphics memory space shared by each VM is overlapped. This paper identifies that the copy overhead caused by GPU context switch is one of the major bottlenecks in performance improvement and proposes a low-overhead dynamic memory management scheme called DymGPU. DymGPU provides two memory allocation algorithms such as size-based and utilization-based algorithms. While the size-based algorithm allocates memory space based on the memory size required by each VM, the utilization-based algorithm considers GPU utilization of each VM to allocate memory space. DymGPU is also dynamic in the sense that the global graphics memory space used by each VM is rearranged at runtime by periodically checking idle VMs and GPU utilization of each runnable VM. We have implemented our proposed approach in gVirt and confirmed that the proposed scheme reduces GPU context switch time by up to 53% and improved the overall performance of various GPU applications by up to 39%.

Сравнительный анализ статических методов верификации динамической памяти

The article provides an overview of the existing methods of dynamic memory verification; a comparative analysis is carried out; the applicability for solving problems of control, monitoring, and verification of dynamic memory is evaluated. This article is divided into eight sections. The first section introduces formal verification, followed by a section that discusses dynamic memory management problems. The third section discusses Hoare's calculus resumed by heap transformations to the stack. The fifth and sixth sections introduce the concept of dynamic memory shape analysis and the rotation of pointers. The seventh is on separation logic. The last section discusses possible areas of further research, particularly the recognition at recording level of various instances of objects; automation of proofs; "hot" code, that is, software code that updates itself when the program runs; expanding intuitiveness, for instance, on proof explanations.

Mpchecker: Use-After-Free Vulnerabilities Protection Based on Multi-Level Pointers

Highly efficient languages, such as C/C++, have low-level control over memory. Due to the lack of validity detection for pointers and garbage collection for memory, developers are responsible for dynamic memory management by explicitly allocating and deallocating memory. However, explicit memory management brings a large number of memory safety-related vulnerabilities, such as use-after-free. The threat of use-after-free vulnerabilities has become more and more serious due to their high level of the severity and quick emergence of the number. In this paper, a dynamic defense system is proposed against use-after-free exploits by introducing an approach based on multi-level pointers that insert intermediate pointers between a heap object and its related pointers. First, the relationship between a heap object to be protected, and the related pointers pointing to it, is established by combing with intermediate pointers. Then, all of the accesses to this object via its related pointers can only be achieved through these intermediate pointers. Finally, to prevent the dangling pointers from being dereferenced to this object, all the intermediate pointers related to this object are invalidated when it is freed so that any access to a freed object can be prevented due to the invalidated intermediate pointers. The prototype system MPChecker is implemented, which can prevent use-after-free exploits for C/C++ multi-threaded programs. Compared with the related methods, MPChecker can protect pointers that are copied in a type-unsafe way from being dereferenced to freed objects. In addition, it can also defend against dangling pointers located on the whole memory, including the stack, the heap, and global memory, rather than the heap only. The defense capability is proved by protecting against two exploits to a real-world program, comparing the support of type-unsafe copy with a self-written program. The performance evaluation of MPChecker with some benchmarks, multi-threaded programs, and real-world programs, shows its comparable efficiency.

Secure and Dynamic Memory Management Architecture for Virtualization Technologies in IoT Devices

The introduction of the internet in embedded devices led to a new era of technology—the Internet of Things (IoT) era. The IoT technology-enabled device market is growing faster by the day, due to its complete acceptance in diverse areas such as domicile systems, the automobile industry, and beyond. The introduction of internet connectivity in objects that are frequently used in daily life raises the question of security—how secure is the information and the infrastructure handled by these devices when they are connected to the internet? Security enhancements through standard cryptographic techniques are not suitable due to the power and performance constraints of IoT devices. The introduction of virtualization technology into IoT devices is a recent development, meant for fulfilling security and performance needs. However, virtualization augments the vulnerability present in IoT devices, due to the addition of one more software layer—namely, the hypervisor, which enables the sharing of resources among different users. This article proposes the adaptation of ASMI (Architectural Support for Memory Isolation—a general architecture available in the literature for the improvement of the performance and security of virtualization technology) on the popular MIPS (Microprocessor without Interlocked Pipeline Stages) embedded virtualization platform, which could be adopted in embedded virtualization architectures for IoT devices. The article illustrates the performance enhancement achieved by the proposed architecture with the existing architectures.

Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis

High-level synthesis (HLS) of field programmable gate array (FPGA)-based accelerators has been proposed in order to simplify accelerator design process with respect to design time and complexity. However, modern HLS tools do not consider dynamic memory allocation constructs in high-level programming languages like C and limit themselves to static memory allocation. This paper proposes a dynamic memory allocation and management scheme, called Hi-DMM, for inclusion in commercial HLS design flows. Hi-DMM performs source-to-source transformation of user C code with dynamic memory constructs into C-source code with the dynamic memory allocator and management scheme developed in this paper. The transformed C-source code is amenable to synthesis by commercial tools like Vivado HLS. Relying on buddy tree-based allocation schemes and efficient hardware implementation of the allocators, Hi-DMM achieves 4x speed-up in both fine-grained and coarse-grained memory allocation compared to previous works. Experimental results obtained by including Hi-DMM with Vivado-HLS show that dynamic memory allocation of FPGA memory resources can be achieved at a much lower latency with minimal resource overhead, paving the way for synthesis of dynamic memory constructs in commercial HLS flows.

A survey of real‐time capabilities in functional languages and compilers

SummaryFunctional programming languages play an important role in the development of correct software systems. As embedded devices become pervasive and perform critical tasks in our lives, their reliability becomes paramount. This presents a natural opportunity to explore the application of functional programming languages to systems that demand highly predictable behavior. In this paper, we explore existing functional programming language compilers and their applicability to real‐time embedded systems. We do this by defining important characteristics needed by a real‐time programming language and survey how well existing languages meet these characteristics. We conduct empirical analysis of language runtimes in order to assess the impact of dynamic memory management on predictability and performance. Lastly, we review different programming models for expressing real‐time considerations in applications.

On Dynamic Scheduling for the GPU and its Applications in Computer Graphics and Beyond.

During the last decade we have witnessed a severe change in computing, as processor clock-rates stopped increasing. Thus, the arguable only way to increase processing power is switching to a parallel computing architecture, like the graphics processing unit (GPU). While a GPU offers tremendous processing power, harnessing this power is often difficult. In our research we tackle this issue, providing various components to allow a wider class of algorithms to execute efficiently on the GPU. These efforts include new processing models for dynamic algorithms with various degrees of parallelism, a versatile task scheduler, based on highly efficient work queues which also support dynamic priority scheduling, and efficient dynamic memory management. Our scheduling strategies advance the state-of-the-art algorithms in the field of rendering, visualization, and geometric modeling. In the field of rendering, we provide algorithms that can significantly speed-up image generation, assigning more processing power to the most important image regions. In the field of geometric modeling we provide the first GPU-based grammar evaluation system that can generate and render cities in real-time which otherwise take hours to generate and could not fit into GPU memory. Finally, we show that mesh processing algorithms can be computed significantly faster on the GPU when parallelizing them with advanced scheduling strategies.

A REVIEW: FUZZY LOGIC CONTROLLER (FLC) IN WIRELESS SENSOR NETWORKS (WSN)

The routing mechanisms are designed to inter-connect the nodes across the networks in dynamic domain. The wireless routing protocols must be empowered with dynamic memory management, which can be deployed with cooperative proactive routing or partial reactive routing mechanisms, which manages the different routing information on run-time memory. The multiple paths can also procured in routing table, which can be used to deploy the load balancing among the multiple paths selected using multipath reactive routing mechanism. In this paper, we have studied the various routing mechanism, which includes the multipath routing, personalized routing, inter-domain routing, joint traffic splitting, rate control mechanism and cognitive heterogeneous routing mechanisms. The comparative study of the latter models is performed, which are observed for their functional merits and demerits. The projected improvement has been observed in the form of segmental routing mechanism, which can handle the micro routes in the inter-domain routing mechanism for WSN.

Evolutionary design of the memory subsystem

The memory hierarchy has a high impact on the performance and power consumption in the system. Moreover, current embedded systems, included in mobile devices, are specifically designed to run multimedia applications, which are memory intensive. This increases the pressure on the memory subsystem and affects the performance and energy consumption. In this regard, the thermal problems, performance degradation and high energy consumption, can cause irreversible damage to the devices.We address the optimization of the whole memory subsystem with three approaches integrated as a single methodology. Firstly, the thermal impact of register file is analyzed and optimized. Secondly, the cache memory is addressed by optimizing cache configuration according to running applications and improving both performance and power consumption. Finally, we simplify the design and evaluation process of general-purpose and customized dynamic memory manager, in the main memory. To this aim, we apply different evolutionary algorithms in combination with memory simulators and profiling tools. This way, we are able to evaluate the quality of each candidate solution and take advantage of the exploration of solutions given by the optimization algorithm. We also provide an experimental experience where our proposal is assessed using well-known benchmark applications.

On dynamic memory allocation in sliding-window parallel patterns for streaming analytics

This work studies the issues related to dynamic memory management in Data Stream Processing, an emerging paradigm enabling the real-time processing of live data streams. In this paper, we consider two streaming parallel patterns and we discuss different implementation variants related to how dynamic memory is managed. The results show that the standard mechanisms provided by modern C++ are not entirely adequate for maximizing the performance. Instead, the combined use of an efficient general purpose memory allocator, a custom allocator optimized for the pattern considered and a custom variant of the C++ shared pointer mechanism, provides a performance improvement up to 16% on the best case.

A Computationally Efficient Implementation of Tabulated Combustion Chemistry based on Polynomials and Automatic Source Code Generation

The simulation of turbulent combustion is a multiphysics and multiscale problem, in which two different domains - fluid mechanics and chemistry - have to be coupled. One solution is a CFD-based simulation framework that performs lookups on tabulated chemistry using flamelets. The tables can become very large when the resolution is increased and modelling parameters and solution values are added. This makes dynamic memory management and its runtime requirements a crucial issue in these simulations. A novel approach for the efficient memory management of tabulated chemistry at reduced computational cost is developed in this study. The original interpolation-focused database is converted into a polynomial description, which is stored in a shared library as a set of functions. This step enables automatic compiler optimization techniques to achieve minimal data movement and the best use of modern computer architecture. The performance and properties of the method are evaluated in a generic test case and a fully coupled flame simulation.

Workload Adaptive Shared Memory Management for High Performance Network I/O in Virtualized Cloud

This paper presents the design and implementation of MemPipe, a dynamic shared memory management system for high performance network I/O among virtual machines (VMs) located on the same host. MemPipe delivers efficient inter-VM communication with three unique features. First, MemPipe employs an inter-VM shared memory pipe to enable high throughput data delivery for both TCP and UDP workloads among co-located VMs. Second, instead of static allocation of shared memories, MemPipe manages its shared memory pipes through a demand driven and proportional memory allocation mechanism, which can dynamically enlarge or shrink the shared memory pipes based on the demand of the workloads in each VM. Third but not the least, MemPipe employs a number of optimizations, such as time-window based streaming partitions and socket buffer redirection, to further optimize its performance. Extensive experiments show that MemPipe improves the throughput of conventional (native) inter VM communication by up to 45 times, reduces the latency by up to 62 percent, and achieves up to 91 percent shared memory utilization.

Improving Dynamic Memory Allocation on Many-Core Embedded Systems With Distributed Shared Memory

Memory management on many-core architectures is a major challenge for improving the overall system performance. Memory resources are distributed over nodes for faster local accesses. Dynamic workloads heavily depend on memory requests and inefficient memory management leads to severe bottlenecks and performance degradation. In this paper, we focus on optimizing dynamic memory allocation on such platforms and present a scalable, microcode-accelerated distributed dynamic memory manager. The proposed manager exploits the presence of a hardware accelerator while offering a C application programming interface to application developers. Experimental results show performance gains on average 10% compared to allocators written purely in C and sufficient scalability as platform size increases.

ABT and SBT Revisited: Efficient Memory Management Techniques for Object Oriented and Web-based Applications

Dynamic memory management is an important and essential part of computer systems design. Efficient memory allocation, garbage collection, and compaction are becoming critical in parallel and distributed applications using object oriented languages like C++ and Java. In addition to achieving fast allocation/de-allocation of memory objects and fragmentation, memory management techniques should strive to improve the overall execution performance of object oriented applications. In this paper, we introduce Address Ordered and Segregated Binary Trees, two memory management techniques particularly efficient for object oriented applications. Our empirical results manifest that both ABT and SBT when accompanied by coalescing outperform existing allocators such as Segregated free lists in terms of storage utilization and execution performance. We also show that these new allocators perform well in terms of storage utilization, even without coalescing. This is in particular suitable for web-applications.

Behaviour and performance comparison between FreeRTOS and µC/OS-III

As the prevalence of embedded systems in various fields has spread, real-time operating systems (RTOSs) have been widely used for many years satisfying real-time requirements and a multitasking design. The use of RTOS adds additional overhead to a system, which should be deliberately considered and evaluated in some critical systems. This paper presents a qualitative and quantitative comparison between an open-source RTOS (FreeRTOS V8.0.0) and a commercial one (?C/OS-III). Both RTOS use a preemptive multitasking kernel, with additional support for round robin scheduling. We aim to benchmark and evaluate their performance and behaviour, including seven performance tests and two behaviour tests. Comparing the measurement results shows that the commercial µC/OS-III does not behave much better than FreeRTOS. Furthermore, we discovered that the priority changing function of µC/OSIII does not behave correctly in some circumstances. Although FreeRTOS has no such problem in the latest version, it still has a problem with its dynamic memory management.