Abstract

This paper presents novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations that are suitable for hard real-time and safety-critical systems due to very high determinism of these operations. The proposed memory manager implements Worst-Fit algorithm for selection of suitable free block of memory that can be used by the external environment, e.g. CPU. The deterministic timing of the memory allocation and deallocation operations is essential for hard real-time systems. The proposed memory manager performs these operations in nearly constant time thanks to the adoption of hardware-accelerated max queue, which is a data structure that continuously provides the largest free block of memory in two clock cycles regardless of actual number or constellation of existing free blocks of memory. In order to minimize the overhead caused by implementing the memory management in hardware, the max queue was optimized by developing a new sorting architecture, called Rocket-Queue. The Rocket-Queue architecture as well as the whole memory manager is described in this paper in detail. The memory manager and the Rocket-Queue architecture were verified using simplified version of UVM and applying billions of randomly generated instructions as testing inputs. The Rocket-Queue architecture was synthesized into Intel FPGA Cyclone V with 100 MHz clock frequency and the results show that it consumes from 17,06% to 38,67% less LUTs than the existing architecture, called Systolic Array. The memory manager implemented in a form of a coprocessor that provides four custom instructions was synthesized into 28nm TSMC HPM technology with 1 GHz clock frequency and 0.9V power supply. The ASIC synthesis results show that the Rocket-Queue based memory manager can occupy up to 24,59% smaller chip area than the Systolic Array based manager. In terms of total power consumption, the Rocket-Queue based memory manager consumes from 15,16% to 42,95% less power.

Highlights

  • Hard real-time (RT) systems belong to a category of cyber-physical and embedded systems that contain real-time tasks

  • The experimental results show that the proposed Rocket-Queue-based dynamic memory manager implementing worst-fit algorithm is scalable regardless of whether it is implemented in FPGA or ASIC technology

  • Novel hardware architecture of the min/max queue, called Rocket-Queue, and hardware architecture of worst-fit based dynamic memory manager was presented in this paper

Read more

Summary

Introduction

Hard real-time (RT) systems belong to a category of cyber-physical and embedded systems that contain real-time tasks. Success of hard real-time tasks depends on the task results but on. AETiC 2019, Vol 3, No 4 time when these tasks are finished too. Improper timing of hard real-time tasks completion (e.g. too late completion) generally represents a big failure as if the task results were incorrect, which may even cause a complete failure of the whole system. It is critically important to consider determinism and predictability of hard RT systems when implementing algorithms for such systems. All operations should be performed in constant or nearly constant time [1, 2]

Results
Discussion
Conclusion
Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call