Dynamic Memory Management Research Articles

Object resizing and reclamation through the use of hardware bit-maps

The memory intensive nature of object-oriented languages such as C++ and Java has created the need of a high-performance dynamic memory management. Object-oriented applications often generate higher memory intensity in the heap region. Thus, high-performance memory manager is needed to cope with such applications. As today's VLSI technology advances, it becomes more and more attractive to map software algorithms such as malloc(), free(), realloc(), and garbage collection into hardware. This paper presents hardware designs of realloc function and sweeping function (for mark and sweep garbage collection) that fully utilize the advantages of combinational logic. In our scheme, the reallocation on the original block can be done in constant time. If the reallocation on the original block is not possible, the previously proposed malloc() and free() can be used to move the contents to a new location. For the sweeping function, the bit-sweeper can detect and sweep the garbage in constant time. Since the sweeping phase often consumes more time than the marking phase, the garbage collection time can be substantially improved. The hardware complexity of proposed scheme (i.e. X-Unit, RS-unit, ESG-unit, and bit-sweeper) is O( n), where n represents the size of bit-map.

Joint scheduling of garbage collector and hard real-time tasks for embedded applications

Programs with complex data structures often require dynamic memory management based on automatic memory reclamation (garbage collection). A major problem in adopting garbage collection for embedded real-time systems is that it often causes unpredictable pauses and that, as a result of such delays, hard real-time tasks may miss their deadlines. In this paper, we propose a new real-time garbage collection technique for embedded applications. In our approach, the system jointly schedules garbage collector and hard real-time tasks using one of the aperiodic server approaches. Our study focuses on reducing memory requirements while guaranteeing the deadlines of hard real-time tasks. To achieve this objective, we model garbage collection requests as aperiodic hard real-time tasks, and schedule them using the sporadic server (SS). We also present an effective live-memory analysis to bound the worst-case garbage collection time. Performance analysis shows that the proposed approach considerably reduces the worst-case memory reservation compared with a background policy. The analytic results are verified by simulation based on trace-driven data.

A study of the allocation behavior of C++ programs

The object-oriented programming (OOP) language systems tend to perform object creation and deletion prolifically. An empirical study has shown that C++ programs can have 10 times more memory allocation and deallocation than comparable C programs. However, the allocation behavior of C++ programs is rarely reported. This paper attempts to locate where the dynamic memory allocations are coming from and report an empirical study of the allocation behavior of C++ programs. Firstly, this paper summarizes the hypothesis of situations that invoke the dynamic memory management explicitly and implicitly. They are: constructors, copy constructors, overloading assignment operator=, type conversions and application-specific member functions. Secondly, the development of a source code level tracing tool is reported as a procedure to investigate the hypothesis. Most of the five C++ programs traced are real-world applications. Thirdly, allocation patterns, object size and age distribution are summarized. Among other things, we found that objects tend to have a very short life-span, and most of them are created through constructors and copy constructors. With these findings, we may improve the performance of dynamic memory management through, a profile-based strategy or reusing objects.

Special issue on ‘Logic Programming and the INTERNET’

Computational logic systems can offer an attractive environment for developing Internet applications. They share many of the important characteristics of popular network programming tools, including dynamic memory management, well-behaved structure and pointer manipulation, robustness, and compilation to architecture-independent bytecode. However, in addition, computational logic systems offer some unique features such as very powerful symbolic processing capabilities, constraint solving, dynamic databases, search facilities, grammars, sophisticated meta-programming, and well understood semantics. Such features can often make it very easy to code simple applications.This special issue concerned with applications is the third of its kind in a journal sponsored by the Association for Logic Programming. The first appeared in 1990, and showed the potential for logic programming to be extended. The second issue highlighted some papers from the Practical Applications of Prolog conference that had been held. This third time, the applications are concerned with the Internet and reflect the profound impact that the Internet has had on the computing landscape.

A simple process for migrating server applications to SMP:s

A strong focus on quality attributes such as maintainability and flexibility has resulted in a number of new methodologies, e.g., object-oriented and component-based design, which can significantly limit the application performance. A major challenge is to find solutions that balance and optimize the quality attributes, e.g., symmetric multiprocessor (SMP) performance contra maintainability and flexibility. We have studied three large real-time telecommunication server applications developed by Ericsson. In all these applications maintainability is strongly prioritized. The applications are also very demanding with respect to performance due to real-time requirements on throughput and response time. SMP:s and multithreading are used in order to give these applications a high and scalable performance. Our main finding is that dynamic memory management is a major bottleneck in these types of applications. The bottleneck can, however, be removed using memory allocators optimized for SMP:s or by reducing the number of allocations. We found that the number of allocations can be significantly reduced by using alternative design strategies for maintainability and flexibility. Based on our experiences we have defined a simple guideline-based process with the aim of helping designers of server applications to establish a balance between SMP performance, maintainability and flexibility.

Dynamic Memory Management in the Loci Framework

Resource management is a critical concern in high-performance computing software. While management of processing resources to increase performance is the most critical, efficient management of memory resources plays an important role in solving large problems. This paper presents a dynamic memory management scheme for a declarative high-performance data-parallel programming system—the Loci framework. In such systems, some sort of automatic resource management is a requirement. We present an automatic memory management scheme that provides good compromise between memory utilization and speed. In addition to basic memory management, we also develop methods that take advantages of the cache memory subsystem and explore balances between memory utilization and parallel communication costs.

Simple data management, scheduling and solution strategies for managing the irregularities in parallel adaptive hp finite element simulations

Adaptive hp finite element methods (FEM), in which both grid size h and local polynomial order p are dynamically altered, generate computations that require dynamic and irregular patterns of data storage, access and computation, making their parallelization very difficult. We show here that such applications can be parallelized easily if we use a good spatially local ordering of all data for organizing storage, distribution and access, and schedule computation using a “owner-computes” rule. This ordering results in a global index space which can be partitioned to distribute the data, locally used in hashing schemes and B-trees for the necessary dynamic memory management, and used in designing efficient solution schemes.

An efficient data structure for dynamic memory management

Advances in software engineering, such as graphical user interface and object-oriented programming, have caused applications to become more memory intensive. The growing popularity of these applications increases the importance of high-performance dynamic memory management. This paper introduces a new data structure intended to increase the efficiency of implementations of common dynamic memory allocation and deallocation algorithms, including First Fit. The data structure, called the Common List, establishes a relationship between the allocated and free list. This strategy increases significantly the deallocation performance. Simulation results based on the traces from publicly available software applications are presented.

SPARP: a single pass antialiased rasterization processor

We present a rasterization processor architecture named SPARP (single-pass antialiased rasterization processor), which exploits antialiased rendering in a single pass. Our architecture is basically based on the A-buffer (Carpenter, Computer graphics 1985;19:69–78) algorithm. We have modified the A-buffer algorithm to enhance the efficiency of hardware implementation and quality of the image rendered, such as the data structure of pixel storage elements, the merging scheme of partial-coverage pixels, and the blending of partial-coverage or non-opaque pixels. For the scan conversion and generation of subpixel masks, we use the representation of edges that was proposed by Schilling (Computer graphics 1991;25:131–41). We represent partial-coverage pixels for a pixel location by a front-to-back sorted list as in the A-buffer and dynamically manage the list storage. We have devised a dynamic memory management scheme that extremely simplifies the memory managing overheads so that we can build it by hard-wired logic circuitry. In our architecture we can render an antialiased scene with the same rendering context of Z-buffer method. Depending on the scene complexity, proposed architecture requires rasterization time 1.4–1.7 times as much as a Z-buffer rasterizer does. The buffer memory requirements can vary depending on the scene complexity; the average storage requirement is 2.75 times that of the Z-buffer for our example scenes. Our architecture can be used with most rendering algorithms to produce high-quality antialiased images at the minimally increased rendering time and buffer memory cost, but due to the improvements in semiconductor technology we can expect that antialiased rasterization processors will be widely adopted in the near future.

Memory management for embedded network applications

In embedded network applications, typically a very large part of the area cost is due to memory units. Also the power for such applications is heavily dominated by the storage and transfers. Given its importance, we have developed a systematic memory management methodology in which the storage related issues are optimized as a first step. In this paper, we present our methodology for embedded network applications. It includes both a dynamic memory management stage, where the data types and virtual memory managers are defined, and a physical memory management stage, where the custom memory architecture is defined. As demonstrated on an industrial example, the application of the methodology results in a heavily power and/or area optimized custom memory architecture for a given application.

A hardware implementation of realloc function

The memory intensive nature of object-oriented languages such as C++ and Java has created the need of a high-performance dynamic memory management. Object-oriented applications often generate higher memory intensity in the heap region. Thus, high-performance memory manager is needed to cope with such applications. As today's VLSI technology advances, it becomes more and more attractive to map basic software algorithms such as malloc( ) , free( ) , and realloc( ) into hardware. This paper presents a hardware design of realloc function that fully utilizes the advantage of combinational logic. There are two steps needed to complete a reallocation process: (a) try to reallocate on the original memory block and (b) if (a) failed, allocate another memory block and copy the contents of the original block to this new location. In our scheme, (a) can be done in constant time. For (b), the allocation of new memory block and the deallocation of original block are done in constant time. The hardware complexity of proposed scheme (i.e. X-unit, RS-unit, and ESG-unit) is O( n), where n represents the size of bit-map.

Matisse: a system-on-chip design methodology emphasizing dynamic memory management

Matisse is a design environment intended for developing systems characterized by a tight interaction between control and data-flow behavior, intensive data storage and transfer and stringent real-time requirements. Matisse bridges the gap from a system specification, using a concurrent object-oriented language, to an optimized embedded single-chip hardware/software implementation. Matisse supports stepwise exploration and refinement of dynamic memory management, memory architecture exploration, and gradual incorporation of timing constraints before going to traditional tools for hardware synthesis, software compilation, and inter-processor communication synthesis. With this approach, specifications of embedded systems can be written in a high-level programming language using data abstraction. Application of Matisse on telecom protocol processing systems in the ATM area shows significant improvements in area usage and power consumption.

Borrow, copy or steal?

Dynamic memory management in C++ is complex, especially across the boundaries of library abstract data types. C++ libraries designed in the orthodox canonical form (OCF) alleviate some of the problems by ensuring that classes which manage any kind of heap structures faithfully copy and delete these. However, in certain common circumstances, OCF heap structures are wastefully copied multiple times. General reference counting is not an option in OCF, since a shared body violates the intended value semantics; although a copy-on-write policy can be made to work with borrowed heap structures. A simpler ownership policy, based on larceny, allows low-level memory manager objects to steal heap structures from temporary variables, in properly isolated circumstances. Various strategies for regulating theft are presented, ranging from pilfer-constructors to locks on heap data. Larceny has similarities with other transfer of ownership patterns, but is more a core implementation technique designed to improve the efficiency and effectiveness of OCF-conformant libraries.

A customisable memory management framework for C++

Automatic garbage collection relieves programmers from the burden of managing memory themselves and several techniques have been developed that make garbage collection feasible in many situations, including real time applications or within traditional programming languages. However, optimal performance cannot always be achieved by a uniform general purpose solution. Sometimes an algorithm exhibits a predictable pattern of memory usage that could be better handled specifically, delaying as much as possible the intervention of the general purpose collector. This leads to the requirement for algorithm specific customisation of the collector strategies. We present a dynamic memory management framework which can be customised to the needs of an algorithm, while preserving the convenience of automatic collection in the normal case. The Customisable Memory Manager (CMM) organises memory in multiple heaps. Each heap is an instance of C++ class which abstracts and encapsulates a particular storage discipline. The default heap for collectable objects uses the technique of mostly copying garbage collection, providing good performance and memory compaction. Customisation of the collector is achieved exploiting object orientation by defining specialised versions of the collector methods for each heap class. The object-oriented interface to the collector enables coexistence and coordination among the various collectors as well as integration with traditional code unaware of garbage collection. The CMM is implemented in C++ without any special support in the language or the compiler. The techniques used in the CMM are general enough to be applicable also to other languages. The performance of the CMM is analysed and compared to other conservative collectors for C/C++ in various configurations. © 1998 John Wiley & Sons, Ltd.

Concurrent fault simulation on message passing multicomputers

Even though hardware accelerators are common in very large scale integration (VLSI) computer-aided design (CAD), fault simulation is a notable exception because of limited availability of memory, the need for dynamic memory management and the complexity of the algorithms themselves. Although simplified fault simulation algorithms that assume a zero delay circuit model can be accelerated, their applicability is limited. Most application specific integrated circuits (ASIC's) designed in industry today have on-chip memory blocks of different dimensions and characteristics, enhancing the complexity of a fault simulator. In this paper, we present a multiple delay algorithm for concurrent fault simulation of logic gates and functional memory blocks. This algorithm has been implemented on the microprogrammable accelerator for rapid simulation (MARS) hardware accelerator system with a 22 MHz clock and a capacity to simulate circuits with millions of devices. Speedup factors of 20 to 30 are easily achieved when compared to software simulators running on comparable hardware platforms and using identical circuit models.

Garbage Collection: Algorithms for Automatic Dynamic Memory Management by Richard Jones and Rafael Lins, John Wiley & Sons, 1996.

<i>Garbage Collection: Algorithms for Automatic Dynamic Memory Management</i> by Richard Jones and Rafael Lins, John Wiley &amp; Sons, 1996.

High-level dynamic memory management for object-oriented real-time systems

Dynamic memory management in real-time systems is difficult because most traditional allocation and deallocation algorithms are unpredictable in terms of their worst-case memory utilization and execution times. This paper describes recent work on a new memory management system designed specifically to support hard-real-time allocation, automatic garbage collection, and defragmentation of the free pool. The memory management system consists of special hardware circuits placed between the CPU's level-two caches and its memory subsystem. Benefits include worst-case allocation delays of two microseconds and typical memory utilizations that exceed binary-buddy allocators by over 30%. A commercial implementation of this technology is currently under development.

An inter-reference gap model for temporal locality in program behavior

The property of locality in program behavior has been studied and modelled extensively because of its application to memory design, code optimization, multiprogramming etc. We propose a k order Markov chain based scheme to model the sequence of time intervals between successive references to the same address in memory during program execution. Each unique address in a program is modelled separately. To validate our model, which we call the Inter-Reference Gap (IRG) model, we show substantial improvements in three different areas where it is applied. (1) We improve upon the miss ratio for the Least Recently Used (LRU) memory replacement algorithm by up to 37%. (2) We achieve up to 22% space-time product improvement over the Working Set (WS) algorithm for dynamic memory management. (3) A new trace compression technique is proposed which compresses up to 2.5% with zero error in WS simulations and up to 3.7% error in the LRU simulations. All these results are obtained experimentally, via trace driven simulations over a wide range of cache traces, page reference traces, object traces and database traces.

Adaptive garbage collection and experiments for implementation

AbstractIn the list processing language, dynamic memory management is indispensable, and hence various methods have been proposed. In one such method, the object is discriminated according to its life, time and garbage collection (GC) is applied efficiently to the unnecessary object, based on a preset “threshold.” A problem is how the threshold should be set in order to realize the most efficient GC.This paper points out that the threshold that realizes the highest efficiency depends on the application to be executed, and proposes the technique of adaptive garbage collection (AGC). An experiment toward its implementation is reported. AGC is a kind of GC which adjusts the threshold dynamically according to memory use, so that efficient operation is realized for a variety of applications. Experiments aiming at the realization of AGC show that applications have their own pace in consuming the memory, and the optimal value of the threshold is related to that pace. It is seen also that the memory‐consuming pace of the application is related closely to the data in the interpreter, leading to the definition of the useful parameter for realizing the efficient AGC.

Parallel simulation today

This paper surveys topics that presently define the state of the art in parallel simulation. Included in the tutorial are discussions on new protocols, mathematical performance analysis, time parallelism, hardware support for parallel simulation, load balancing algorithms, and dynamic memory management for optimistic synchronization.