Dynamic Instruction Research Articles

An XOR‐based parameterization for instruction register files

The instruction register file (IRF) shortens and obfuscates instruction sequences by compressing multiple instructions into a packed instruction. The IRF could improve its efficiency by parameterization, but the previously proposed parameterization techniques did not extract the similarity of instructions well. In this paper, we propose an XOR‐based parameterization to utilize the limited capacity of the IRF more efficiently. According to our evaluation, with an improved algorithm of instruction selection, our approach makes 20.2% more dynamic instructions IRF‐resident than the previous techniques. It also reduces the number of instruction fetches from the cache by 6.3% on average. We also confirmed that the hardware overhead of our parameterization was about a quarter of the previous one. © 2015 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

Studying Optimal Spilling in the Light of SSA

Recent developments in register allocation, mostly linked to static single assignment (SSA) form, have shown the benefits of decoupling the problem in two phases: a first spilling phase places load and store instructions so that the register pressure at all program points is small enough, and a second assignment and coalescing phase maps the variables to physical registers and reduces the number of move instructions among registers. This article focuses on the first phase, for which many open questions remain: in particular, we study the notion of optimal spilling (what can be expressed?) and the impact of SSA form (does it help?). To identify the important features for optimal spilling on load-store architectures, we develop a new integer linear programming formulation, more accurate and expressive than previous approaches. Among other features, we can express SSA ϕ-functions, memory-to-memory copies, and the fact that a value can be stored simultaneously in a register and in memory. Based on this formulation, we present a thorough analysis of the results obtained for the SPECINT 2000 and EEMBC 1.1 benchmarks, from which we draw, among others, the following conclusions: (1) rematerialization is extremely important; (2) SSA complicates the formulation of optimal spilling, especially because of memory coalescing when the code is not in conventional SSA (CSSA); (3) microarchitectural features are significant and thus have to be accounted for; and (4) significant savings can be obtained in terms of static spill costs, cache miss rates, and dynamic instruction counts.

Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance

Superscalar in-order processors form an interesting alternative to out-of-order processors because of their energy efficiency and lower design complexity. However, despite the reduced design complexity, it is nontrivial to get performance estimates or insight in the application--microarchitecture interaction without running slow, detailed cycle-level simulations, because performance highly depends on the order of instructions within the application’s dynamic instruction stream, as in-order processors stall on interinstruction dependences and functional unit contention. To limit the number of detailed cycle-level simulations needed during design space exploration, we propose a mechanistic analytical performance model that is built from understanding the internal mechanisms of the processor. The mechanistic performance model for superscalar in-order processors is shown to be accurate with an average performance prediction error of 3.2% compared to detailed cycle-accurate simulation using gem5. We also validate the model against hardware, using the ARM Cortex-A8 processor and show that it is accurate within 10% on average. We further demonstrate the usefulness of the model through three case studies: (1) design space exploration, identifying the optimum number of functional units for achieving a given performance target; (2) program--machine interactions, providing insight into microarchitecture bottlenecks; and (3) compiler--architecture interactions, visualizing the impact of compiler optimizations on performance.

Effects of Cooperative E-Learning on Learning Outcomes

This study aims to discuss the effects of E-Learning and cooperative learning on learning outcomes. E-Learning covers the dimensions of Interpersonal communication, abundant resources, Dynamic instruction, and Learning community; and, cooperative learning contains three dimensions of Cooperative motive, Social interaction, and Cognition construction. Teachers and students in ten public and private universities in southern Taiwan are selected as the research subjects. Total 500 questionnaires are distributed and collected on-site, and 327 valid copies are retrieved with the retrieval rate 65%. The research finding show partially significant correlations between E-Learning and cooperative learning, between cooperative learning and learning outcomes, and between E-Learning and learning outcomes. Finally, several suggestions are proposed for teachers in E-Learning and cooperative learning.

Branch Prediction-Directed Dynamic Instruction Cache Locking for Embedded Systems

Cache locking is a cache management technique to preclude the replacement of locked cache contents. Cache locking is often adopted to improve cache access predictability in Worst-Case Execution Time (WCET) analysis. Static cache locking methods have been proposed recently to improve Average-Case Execution Time (ACET) performance. This article presents an approach, Branch Prediction-directed Dynamic Cache Locking (BPDCL), to improve system performance through cache conflict miss reduction. In the proposed approach, the control flow graph of a program is first partitioned into disjoint execution regions, then memory blocks worth locking are determined by calculating the locking profit for each region. These two steps are conducted during compilation time. At runtime, directed by branch predictions, locking routines are prefetched into a small high-speed buffer. The predetermined cache locking contents are loaded and locked at specific execution points during program execution. Experimental results show that the proposed BPDCL method exhibits an average improvement of 25.9%, 13.8%, and 8.0% on cache miss rate reduction in comparison to cases with no cache locking, the static locking method, and the dynamic locking method, respectively.

Dynamic Thermal Estimation Methodology for High-Performance 3-D MPSoC

In 3-D integrated circuits, accurate runtime sensing of on-chip temperature is required to establish dynamic thermal management instruction sets. Placement restrictions and excessive runtime thermal variations, however, compromise the performance and reliability of the sensor readings. Within this framework, a novel methodology for thermal estimation based on unscented Kalman filter, augmented only with a limited number of temperature sensors at a few selected locations, is proposed. In addition, we extend discontinuous Galerkin finite-element method to include coupling mechanism between neighboring grid cells for accurate thermal profile estimation and introduce a balanced stochastic truncation to find a low-dimensional but accurate approximation of the thermal network over the whole frequency domain. As the experimental results show, the runtime thermal estimation method reduces temperature estimation errors by an order of magnitude.

Improving JavaScript performance by deconstructing the type system

Increased focus on JavaScript performance has resulted in vast performance improvements for many benchmarks. However, for actual code used in websites, the attained improvements often lag far behind those for popular benchmarks. This paper shows that the main reason behind this short-fall is how the compiler understands types. JavaScript has no concept of types, but the compiler assigns types to objects anyway for ease of code generation. We examine the way that the Chrome V8 compiler defines types, and identify two design decisions that are the main reasons for the lack of improvement: (1) the inherited prototype object is part of the current object's type definition, and (2) method bindings are also part of the type definition. These requirements make types very unpredictable, which hinders type specialization by the compiler. Hence, we modify V8 to remove these requirements, and use it to compile the JavaScript code assembled by JSBench from real websites. On average, we reduce the execution time of JSBench by 36%, and the dynamic instruction count by 49%.

WCET

Caches are widely used in embedded systems to bridge the increasing speed gap between processors and off-chip memory. However, caches make it significantly harder to compute the WCET(Worst Case Execution Time) of a task. To alleviate this problem, cache locking has been proposed. We investigate the I-cache locking problem, and propose a WCET-aware, min-cut based dynamic instruction cache locking approach for reducing the WCET of a single task. We have implemented our approach and compared it with the two state-of-the-art cache locking approaches by using a set of benchmarks from the MRTC benchmark suite. The experimental results show that our approach achieves the average improvements of 41%, 15% and 7% over the partial locking approach for the 256B, 512B and 1KB caches, respectively, and 7%, 18% and 17% over the longest path based dynamic locking approach for the 256B, 512B and 1KB caches, respectively.

Efficient Spatial Processing Element Control via Triggered Instructions

In this article, the authors present triggered instructions, a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transition concisely between states without explicit branch instructions. They also allow efficient reactivity to inter-PE communication traffic. The approach provides a unified mechanism to avoid overserialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading, which each require distinct hardware mechanisms in a traditional sequential architecture.

Performance Comparison between LLVM and GCC Compilers for the AE32000 Embedded Processor

The embedded processor market has grown rapidly and consistently with the appearance of mobile devices. In an embedded system, the power consumption and execution time are important factors affecting the performance. The system performance is determined by both hardware and software. Although the hardware architecture is high-end, the software runs slowly due to the low quality of codes. This study compared the performance of two major compilers, LLVM and GCC on a32-bit EISC embedded processor. The dynamic instructions and static code sizes were evaluated from these compilers with the EEMBC benchmarks.LLVM generally performed better in the ALU intensive benchmarks, whereas GCC produced a better register allocation and jump optimization. The dynamic instruction count and static code of GCC were on average 8% and 7% lower than those of LLVM, respectively.

Integrating the audience into a theatre performance using mobile devices

Purpose – Theatre Engine is a three-phase project exploring the integration of mobile devices such as smart phones and tablet computers as user interaction mechanisms for live theatrical performances. This paper aims to describe the technical details for the first performance in the series: transitions, including system design, user interface details, and lessons learned. Design/methodology/approach – The Theatre Engine project consists of a network of mobile Android-based devices that communicate with a server managing a live theatrical performance. Additional systems provide projected graphics within the performance space, dynamic instructions to live musicians, and control of theatrical equipment including robotic lighting. The system is under the live control of a stage managers and show runner. The first phase produced the performance transitions, where live and virtual dancers interacted with audience members. Findings – The user activities are described in the context of manipulations and the effec...

A transparent and adaptive reconfigurable system

In the current scenario, where computer systems are characterized by a high diversity of applications coexisting in a single device, and with the stagnation in frequency scaling because of the excessive power dissipation, reconfigurable systems have already proven to be very effective. However, they all present two major drawbacks, which are addressed by this work: lack of transparency (the need for special tools or compilers that changes the original code) and no ability to adapt to applications with different behaviors and characteristics, so significant gains are achieved only in very specific data stream oriented applications. Therefore, this work proposes the Dynamic Instruction Merging (DIM), a Binary Translation mechanism responsible for transforming sequences of instructions into a coarse-grained array configuration at run-time, in a totally transparent process, with support to speculative execution. The proposed system does not impose any kind of modification to the source or binary codes, so full binary compatibility is maintained. Moreover, it can optimize any application, even those that do not present specific kernels for optimization. DIM presents, on average, 2.7 times of performance gains and 2.35 times of energy savings over a MIPS processor, and a higher IPC than an out-of-order superscalar processor, running the MIBench benchmark set.

Highway Toll Free Release Queue Length Quantitative Algorithm Based on 3G/4G Intelligent Monitoring System

In this paper, on the basis of queuing theory, a quantitative algorithm of highway toll free release length using 3G/4G intelligent monitoring system is proposed in view of congestion problems of the domestic highway toll. In the algorithm, the severity of real-time congestion is divided into three levels, each level corresponds to different queue length thresholds; The central server of monitoring system can determine the congestion level at present and give the dynamic free release queue length instructions using the algorithm; Computer simulation shows that the algorithm has certain practical guiding significance.

Preventive and Cautionary Dynamics in the Symphonies of Mendelssohn and his Time

From the late eighteenth century onward, composers began to use dynamic signs as an independent layer of expressive meaning, deployed either to reinforce the dynamic tendencies inherent in the music (through melodic or harmonic trajectory, phrasing, texture, etc.) or to counteract them. The study of this phenomenon thus far has been limited to individual observations regarding particular events, such as “surprise dynamics” (for example sudden peaks in volume or a subito piano following a crescendo), with no attempt to reach a systematic understanding. This article elucidates a little-noticed device, the preventive or cautionary dynamic. Some nineteenth-century composers reiterate dynamic instructions in their instrumental music several times in succession. The purpose of these repetitions is to maintain a desired dynamic level that runs counter to the intrinsic ebb and flow of tonal music (the “internal dynamic” as defined by some authors). The device is used most frequently at the extremes of the dynamic spectrum, often to create expressive tension in a poetic/extramusical sense. The first composer to make substantial use of this technique was Beethoven, but it is Mendelssohn who developed and deployed it most fully. This type of dynamic instruction is most prevalent in large-scale instrumental compositions, such as the symphony, and highlights another aspect of musical practice of the period: composers increasingly had to contend with conductors and performances over which they had no direct control. The increased use of dynamic signs in general and preventive or cautionary dynamics in particular can thus be read as an attempt to assert control over expressive aspects of their compositions that traditionally had been left to performers.

Reducing Power in Processor Unit via Centralized Dynamic Resource Size Management

In Microprocessor power minimization is a major concern. Many circuit and micro-architectural innovations have been proposed to reduce power in many individual processor units. The strategy is used to dynamically and simultaneously adjust the reorder buffer to reduce power dissipation in the data path without significant impact on the performance. Therefore a challenge is to find a centralized approach which can address power issues for one unit with the least amount of redesign and verification efforts and the least hardware overhead. Therefore it proposes such a centralized approach that attempts to simultaneously reduce power in processor unit with highest dissipation in reorder buffer. It is based on an observation that utilization varies significantly, during cache miss period. Some of the superscalar processors, such as the Intel processor implement physical registers using the Reorder Buffer (ROB) slots. One of the main dynamic instruction scheduling artifacts used in such datapath designs is the Reorder Buffer (ROB), which is used to recover to a precise state when interrupts or branch mispredictions occur. One of the power reduction technique used in ROB is dynamic resizing.

A comparison of instruction memories from the WCET perspective

Abstract Hard real-time systems demand high performance in combination with a timing predictable program execution. The performance of a system in the worst-case, represented by its worst case execution time (WCET), highly depends on the design of the memory subsystem. In this paper we focus on the instruction memory hierarchy and quantify the impact of different on-chip instruction memories on the worst-case timing of the system. A function-based dynamic instruction scratchpad (D-ISP), an instruction cache, and static instruction scratchpads using basic-block-based and function-based assignment algorithms are compared. Therefore, we provide WCET bounds for systems with different on-chip instruction memories and different off-chip memory timings. We show that for small memory sizes a static instruction scratchpad usually outperforms the other memories in terms of the WCET estimate. However, with increasing memory sizes the D-ISP is able to reach lower WCET bounds. An instruction cache can only provide lower WCET bounds than the other memories, if no suitable assignment for the static instruction scratchpads is found or if the D-ISP suffers from thrashing or frequently loads unused code.

An energy-efficient method of supporting flexible special instructions in an embedded processor with compact ISA

In application-specific processor design, a common approach to improve performance and efficiency is to use special instructions that execute complex operation patterns. However, in a generic embedded processor with compact Instruction Set Architecture (ISA), these special instructions may lead to large overhead such as: ( i ) more bits are needed to encode the extra opcodes and operands, resulting in wider instructions; ( ii ) more Register File (RF) ports are required to provide the extra operands to the function units. Such overhead may increase energy consumption considerably. In this article, we propose to support flexible operation pair patterns in a processor with a compact 24-bit RISC-like ISA using: ( i ) a partially reconfigurable decoder that exploits the pattern locality to reduce opcode space requirement; ( ii ) a software-controlled bypass network to reduce operand encoding bit and RF port requirement. An energy-aware compiler backend is designed for the proposed architecture that performs pattern selection and bypass-aware scheduling to generate energy-efficient codes. Though the proposed design imposes extra constraints on the operation patterns, the experimental results show that for benchmark applications from different domains, the average dynamic instruction count is reduced by over 25%, which is only about 2% less than the architecture without such constraints. The proposed architecture reduces total energy by an average of 15.8% compared to the RISC baseline, while the one without constraints achieves almost no improvement due to its high overhead. When high performance is required, the proposed architecture is able to achieve a speedup of 13.8% with 13.1% energy reduction compared to the baseline by introducing multicycle SFU operations.

Design exploration of a NVM based hybrid instruction memory organization for embedded platforms

Non volatile memory (NVM) technologies are being explored extensively to replace conventional SRAM based memories. The main focus of this paper is the exploration of a NVM based instruction memory in low power embedded systems for wireless or multimedia target applications. A SRAM based traditional instruction memory organization suitable for the target applications is taken as the base. Different Resistive RAM (ReRAM) based organizations are then designed as alternatives keeping in mind their limitations (write process related), and energy and performance trade-offs. The NVM array design is explored and optimized based on energy and performance trade-offs. Dynamic instruction mapping and architectural design changes are utilized to minimize ReRAM limitations and maximize its positive contributions. Energy and performance values are obtained by extension of CACTI models, Spice and VHDL simulations. The best ReRAM based hybrid instruction memory organization that utilizes our proposed methodology showed significantly lower energy consumption (up-to 82.07 % read energy reduction) even in case of 0 % performance penalty.

Triggered instructions

In this paper, we present triggered instructions , a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transition concisely between states without explicit branch instructions. They also allow efficient reactivity to inter-PE communication traffic. The approach provides a unified mechanism to avoid over-serialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading, which each require distinct hardware mechanisms in a traditional sequential architecture. Our analysis shows that a triggered-instruction based spatial accelerator can achieve 8X greater area-normalized performance than a traditional general-purpose processor. Further analysis shows that triggered control reduces the number of static and dynamic instructions in the critical paths by 62% and 64% respectively over a program-counter style spatial baseline, resulting in a speedup of 2.0X.

The quadratically damped oscillator: A case study of a non-linear equation of motion

The equation of motion for a quadratically damped oscillator, where the damping is proportional to the square of the velocity, is a non-linear second-order differential equation. Non-linear equations of motion such as this are seldom addressed in intermediate instruction in classical dynamics; this one is problematic because it cannot be solved in terms of elementary functions. Like all second-order ordinary differential equations, it has a corresponding first-order partial differential equation, whose independent solutions constitute the constants of the motion. These constants readily provide an approximate solution correct to first order in the damping constant. They also reveal that the quadratically damped oscillator is never critically damped or overdamped, and that to first order in the damping constant the oscillation frequency is identical to the natural frequency. The technique described has close ties to standard tools such as integral curves in phase space and phase portraits.