Dynamic Instruction Research Articles

Self-efficacy and problem-solving skills in mathematics: the effect of instruction-based dynamic versus static visualization

ABSTRACT This study explores the self-efficacy and problem-solving skills of middle school mathematics students. The students – 111 9th graders who were studying a unit for the analysis of function – were given mathematics instruction that was based on either dynamic or static visualization. Findings revealed a positive impact of instruction that was based on dynamic visualization that involved the use of the technological GeoGebra application, compared to instruction that was based on static visualization. The students who were exposed to dynamic visualization instruction displayed high levels of mathematics self-efficacy in real time. Improvement in the mathematics problem-solving skills of these students was shown both immediately after the intervention and three months later, demonstrating better conceptual and procedural understanding. The findings imply that exposure to instruction-based dynamic visualization contributed to closing both the affective and cognitive gaps between high and low achievers. The study offers a significant contribution to theoretical and methodological aspects, and provides practical understanding of instruction-based dynamic visualization about performance of mathematics students in both the affective and cognitive domains.

Multi-objective Exploration for Practical Optimization Decisions in Binary Translation

In the design of mobile systems, hardware/software (HW/SW) co-design has important advantages by creating specialized hardware for the performance or power optimizations. Dynamic binary translation (DBT) is a key component in co-design. During the translation, a dynamic optimizer in the DBT system applies various software optimizations to improve the quality of the translated code. With dynamic optimization, optimization time is an exposed run-time overhead and useful analyses are often restricted due to their high costs. Thus, a dynamic optimizer needs to make smart decisions with limited analysis information, which complicates the design of optimization decision models and often causes failures in human-made heuristics. In mobile systems, this problem is even more challenging because of strict constraints on computing capabilities and memory size. To overcome the challenge, we investigate an opportunity to build practical optimization decision models for DBT by using machine learning techniques. As the first step, loop unrolling is chosen as the representative optimization. We base our approach on the industrial strength DBT infrastructure and conduct evaluation with 17,116 unrollable loops collected from 200 benchmarks and real-life programs across various domains. By utilizing all available features that are potentially important for loop unrolling decision, we identify the best classification algorithm for our infrastructure with consideration for both prediction accuracy and cost. The greedy feature selection algorithm is then applied to the classification algorithm to distinguish its significant features and cut down the feature space. By maintaining significant features only, the best affordable classifier, which satisfies the budgets allocated to the decision process, shows 74.5% of prediction accuracy for the optimal unroll factor and realizes an average 20.9% reduction in dynamic instruction count during the steady-state translated code execution. For comparison, the best baseline heuristic achieves 46.0% prediction accuracy with an average 13.6% instruction count reduction. Given that the infrastructure is already highly optimized and the ideal upper bound for instruction reduction is observed at 23.8%, we believe this result is noteworthy.

ПРАКТИЧНІ ЗАНЯТТЯ З СУСПІЛЬСТВОЗНАВСТВА – ТВОРЧА МАЙСТЕРНЯ КОМПЕТЕНТНОГО УЧНЯ

The author describes the importance of the development of creativity, which has a positive impact on the successful life with individually oriented and competence approach. The author places so much emphasis on the analysis of conceptual questions of practical exercises of Social Studies as creative workshops of competent students. The article notes the importance of the development of conceptual thinking, skills for analyzing the events and phenomena of life and educational situations. A mentally creative innovator is flexible, in depth and broad-mindedness, an in affective way of resolving problems. In that process, it is important to develop emotional and logical thinking of pupils, fantasies, their abilities to imagine by using curricular and cross-curricular links, verbal educational and figurative methods. The variety of methods, techniques, teaching facilities are contributed to the motivation of students.The importance of the practical exercise to the development of creative work is determined. This is an education of workshop of the enhance abilities and skills, enrichment of the lessons learned by original methods of solutions system-inherent challenges in the process of creative and cognitive activities.The model watershed-course of the practical exercises provides the development of a problematic situation, the formulation of the thematic, crucial and semantic problems, the mainstream of the knowledge and skills, formulating assumption, purposes, plans, choose ways of achieving aims (introductory part), the creative-search activities, the solutions of the system-inherent challenges, the formation of an unique method activities (each lesson), the responses and analyses of the results, the auto-evaluation and self-evaluation (concluding part).The students’ creative activity allows a considerable degree of freedom, the coordination and advising of the teachers’ function to joint activities of the form and characterized by a creative approach to training, the establishment of a dynamic instruction.

Exposing Memory Access Patterns to Improve Instruction and Memory Efficiency in GPUs

Modern computing workloads often have high memory intensity, requiring high bandwidth access to memory. The memory request patterns of these workloads vary and include regular strided accesses and indirect (pointer-based) accesses. Such applications require a large number of address generation instructions and a high degree of memory-level parallelism. This article proposes new memory instructions that exploit strided and indirect memory request patterns and improve efficiency in GPU architectures. The new instructions reduce address calculation instructions by offloading addressing to dedicated hardware, and reduce destructive memory request interference by grouping related requests together. Our results show that we can eliminate 33% of dynamic instructions across 16 GPU benchmarks. These improvements result in an overall runtime improvement of 26%, an energy reduction of 18%, and a reduction in energy-delay product of 32%.

An empirical study of the effect of source-level loop transformations on compiler stability

Modern compiler optimization is a complex process that offers no guarantees to deliver the fastest, most efficient target code. For this reason, compilers struggle to produce a stable performance from versions of code that carry out the same computation and only differ in the order of operations. This instability makes compilers much less effective program optimization tools and often forces programmers to carry out a brute force search when tuning for performance. In this paper, we analyze the stability of the compilation process and the performance headroom of three widely used general purpose compilers: GCC, ICC, and Clang. For the study, we extracted over 1,000 <pre>for</pre> loop nests from well-known benchmarks, libraries, and real applications; then, we applied sequences of source-level loop transformations to these loop nests to create numerous semantically equivalent mutations ; finally, we analyzed the impact of transformations on code quality in terms of locality, dynamic instruction count, and vectorization. Our results show that, by applying source-to-source transformations and searching for the best vectorization setting, the percentage of loops sped up by at least 1.15x is 46.7% for GCC, 35.7% for ICC, and 46.5% for Clang, and on average the potential for performance improvement is estimated to be at least 23.7% for GCC, 18.1% for ICC, and 26.4% for Clang. Our stability analysis shows that, under our experimental setup, the average coefficient of variation of the execution time across all mutations is 18.2% for GCC, 19.5% for ICC, and 16.9% for Clang, and the highest coefficient of variation for a single loop nest reaches 118.9% for GCC, 124.3% for ICC, and 110.5% for Clang. We conclude that the evaluated compilers need further improvements to claim they have stable behavior.

Investigation of the effectiveness of common representational formats in online learner-paced software training materials

ABSTRACT The popularity of online learning has made web-based software training materials the primary learning resources adopted by computer users. Thus, this study aimed to investigate the effectiveness of various common representational formats of web-based instructions. The formats included static (textual manual with screenshots) and dynamic (animated demonstration, AD) instructions. The findings suggested that in learner-paced learning with sufficient learning time (a) both narrated and captioned AD formats tended to increase transfer performance; (b) the segmenting principle likely became less important for the static format; and (c) the modality principle likely became less important for the AD format. Implications for determining optimal AD segment length for student engagement and suggestions for possible factors to be included in future research are offered accordingly.

Malware Family Discovery Using Reversible Jump MCMC Sampling of Regimes

ABSTRACTMalware is computer software that has either been designed or modified with malicious intent. Hundreds of thousands of new malware threats appear on the internet each day. This is made possible through reuse of known exploits in computer systems that have not been fully eradicated; existing pieces of malware can be trivially modified and combined to create new malware, which is unknown to anti-virus programs. Finding new software with similarities to known malware is therefore an important goal in cyber-security. A dynamic instruction trace of a piece of software is the sequence of machine language instructions it generates when executed. Statistical analysis of a dynamic instruction trace can help reverse engineers infer the purpose and origin of the software that generated it. Instruction traces have been successfully modeled as simple Markov chains, but empirically there are change points in the structure of the traces, with recurring regimes of transition patterns. Here, reversible jump Markov chain Monte Carlo for change point detection is extended to incorporate regime-switching, allowing regimes to be inferred from malware instruction traces. A similarity measure for malware programs based on regime matching is then used to infer the originating families, leading to compelling performance results.

Enabling SIMT Execution Model on Homogeneous Multi-Core System

Single-instruction multiple-thread (SIMT) machine emerges as a primary computing device in high-perfor-mance computing, since the SIMT execution paradigm can exploit data-level parallelism effectively. This article explores the SIMT execution potential on homogeneous multi-core processors, which generally run in multiple-instruction multiple-data (MIMD) mode when utilizing the multi-core resources. We address three architecture issues in enabling SIMT execution model on multi-core processor, including multithreading execution model, kernel thread context placement, and thread divergence. For the SIMT execution model, we propose a fine-grained multithreading mechanism on an ARM-based multi-core system. Each of the processor cores stores the kernel thread contexts in its L1 data cache for per-cycle thread-switching requirement. For divergence-intensive kernels, an Inner Conditional Statement First (ICS-First) mechanism helps early re-convergence to occur and significantly improves the performance. The experiment results show that effectiveness in data-parallel processing reduces on average 36% dynamic instructions, and boosts the SIMT executions to achieve on average 1.52× and up to 5× speedups over the MIMD counterpart for OpenCL benchmarks for single issue in-order processor cores. By using the explicit vectorization optimization on the kernels, the SIMT model gains further benefits from the SIMD extension and achieves 1.71× speedup over the MIMD approach. The SIMT model using in-order superscalar processor cores outperforms the MIMD model that uses superscalar out-of-order processor cores by 40%. The results show that, to exploit data-level parallelism, enabling the SIMT model on homogeneous multi-core processors is important.

SOFRITAS

Correctly synchronizing multithreaded programs is challenging and errors can lead to program failures such as atomicity violations. Existing strong memory consistency models rule out some possible failures, but are limited by depending on programmer-defined locking code. We present the new Ordering-Free Region (OFR) serializability consistency model that ensures atomicity for OFRs, which are spans of dynamic instructions between consecutive ordering constructs (e.g., barriers), without breaking atomicity at lock operations. Our platform, Serializable Ordering-Free Regions for Increasing Thread Atomicity Scalably (SOFRITAS), ensures a C/C++ program's execution is equivalent to a serialization of OFRs by default. We build two systems that realize the SOFRITAS idea: a concurrency bug finding tool for testing called SOFRITEST, and a production runtime system called SOPRO. SOFRITEST uses OFRs to find concurrency bugs, including a multi-critical-section atomicity violation in memcached that weaker consistency models will miss. If OFR's are too coarse-grained, SOFRITEST suggests refinement annotations automatically. Our software-only SOPRO implementation has high performance, scales well with increased parallelism, and prevents failures despite bugs in locking code. SOFRITAS has an average overhead of just 1.59x on a single-threaded execution and 1.51x on sixteen threads, despite pthreads' much weaker memory model.

Enhance virtual-machine-based code obfuscation security through dynamic bytecode scheduling

Code virtualization built upon virtual machine (VM) technologies is emerging as a viable method for implementing code obfuscation to protect programs against unauthorized analysis. State-of-the-art VM-based protection approaches use a fixed scheduling structure where the program always follows a single, deterministic execution path for the same input. Such approaches, however, are vulnerable in certain scenarios where the attacker can reuse knowledge extracted from previously seen software to crack applications protected with the same obfuscation scheme. This paper presents Dsvmp, a novel VM-based code obfuscation approach for software protection. Dsvmp brings together two techniques to provide stronger code protection than prior VM-based approaches. Firstly, it uses a dynamic instruction scheduler to randomly direct the program to execute different paths without violating the correctness across different runs. By randomly choosing the program execution path, the application exposes diverse behavior, making it much more difficult for an attacker to reuse the knowledge collected from previous runs or similar applications to launch an attack. Secondly, it employs multiple VMs to further obfuscate the mapping from VM opcode to native machine instructions, so that the same opcode could be mapped to different native instructions at runtime, making code analysis even harder. We have implemented Dsvmp in a prototype system and evaluated it using a set of widely used applications. Experimental results show that Dsvmp provides stronger protection with comparable runtime overhead and code size, when it is compared to two commercial VM-based code obfuscation tools.

Dynamic Instructions in Check-All-That-Apply Questions

Check-all-that-apply questions are one of the most commonly used question formats in self-administered surveys. They are especially valuable because they allow respondents to select several responses from a list of alternatives that they consider applicable. In this study, we assessed the effectiveness of different types of instructions requesting a specific number of responses to a check-all-that-apply question in a web survey. We compared “static” instructions that are always visible together with the question stem, “dynamic” instructions that instantly appear once respondents start answering the question, and “combined” instructions taking advantage of both static and dynamic instructions. Findings showed that in view of respondent compliance with the instruction, the combination of a static and dynamic instruction is most effective. However, findings also revealed that the specific number of responses requested in the instruction has to be taken into account as a decisive factor influencing the response selection process and ultimately data quality.

Malware algorithm classification method based on big data analysis

Internet technology has greatly increased the number of malware attacks on networks. Consequently, it has also elevated the importance of automatic malware detection and classification technology based on big data analysis in the field of information security. This paper presents a new method for classifying malware algorithms that exhibits both high accuracy and high coverage. The method combines big data analysis with software security technologies such as feature extraction, machine learning, binary instrumentation and dynamic instruction flow analysis to achieve automated classification of malware algorithms. 20 classification experiments prove the correctness of the method. We also discuss future directions for improving the method.

Malware Algorithm Classification Method Based on Big Data Analysis

Internet technology has greatly increased the number of malware attacks on networks. Consequently, it has also elevated the importance of automatic malware detection and classification technology based on big data analysis in the field of information security. This paper presents a new method for classifying malware algorithms that exhibits both high accuracy and high coverage. The method combines big data analysis with software security technologies such as feature extraction, machine learning, binary instrumentation and dynamic instruction flow analysis to achieve automated classification of malware algorithms. 20 classification experiments prove the correctness of the method. We also discuss future directions for improving the method.

1G09 複素数平面の学習における動的教材の活用 : ICTによる数学導入教育の教材作り((04)教材の開発-II,口頭発表)

1G09 複素数平面の学習における動的教材の活用 : ICTによる数学導入教育の教材作り((04)教材の開発-II,口頭発表)

The Capacity for Simulation by Physical Modeling to Elicit Perceptual Differences Between Trumpet Sounds

This paper investigates the subjects' ability to perceive trumpet sound changes, the sounds being either simulated by physical modeling or played by a real musician. The objective of the paper is to study to what extent simulations are able to create perceptually distinct sounds and to compare the discrimination on simulated sounds to the discrimination obtained when the instrument is played. Two experimental factors are considered to study perceptual discriminations by a panel of subjects: changes in the resonator geometry (instrument discrimination) and changes in the sound dynamics of the same instrument (dynamics discrimination). The changes in the resonator geometry are made with tiny geometrical variations of a parameterized leadpipe, whereas changes in dynamics are generated modifying control parameters for simulated sounds and playing dynamic instructions for real musicians. The same note (Bb4) is simulated using the harmonic balance technique and played by a real musician. To assess the discrimination, a same-different test has been carried out involving a panel of 24 listeners and pairs of sounds coming from the simulations or the recordings (for the sake of the experiment, the recorded sounds are resynthesized). For the different experimental conditions (differences between trumpets or between dynamics), the abilities of the listener to discriminate different sounds and to identify identical sounds are analyzed. Using the Receiver Operating Characteristics plots, the results show that even if the differences are more noticeable with sounds played by the musician, simulations are able to produce noticeable differences between the instruments, mainly due to playing frequency differences. They confirm the capacity of the physical model to represent realistic playing conditions for the trumpet.

Hardware-Accelerated Cross-Architecture Full-System Virtualization

Hardware virtualization solutions provide users with benefits ranging from application isolation through server consolidation to improved disaster recovery and faster server provisioning. While hardware assistance for virtualization is supported by all major processor architectures, including Intel, ARM, PowerPC, and MIPS, these extensions are targeted at virtualization of the same architecture, for example, an x86 guest on an x86 host system. Existing techniques for cross-architecture virtualization, for example, an ARM guest on an x86 host, still incur a substantial overhead for CPU, memory, and I/O virtualization due to the necessity for software emulation of these mismatched system components. In this article, we present a new hardware-accelerated hypervisor called C aptive , employing a range of novel techniques that exploit existing hardware virtualization extensions for improving the performance of full-system cross-platform virtualization. We illustrate how (1) guest memory management unit (MMU) events and operations can be mapped onto host memory virtualization extensions, eliminating the need for costly software MMU emulation, (2) a block-based dynamic binary translation engine inside the virtual machine can improve CPU virtualization performance, (3) memory-mapped guest I/O can be efficiently translated to fast I/O specific calls to emulated devices, and (4) the cost for asynchronous guest interrupts can be reduced. For an ARM-based Linux guest system running on an x86 host with Intel VT support, we demonstrate application performance levels, based on SPEC CPU2006 benchmarks, of up to 5.88× over state-of-the-art Q emu and 2.5× on average, achieving a guest dynamic instruction throughput of up to 1280 MIPS (million instructions per second) and 915.52 MIPS, on average.

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control

Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures

There has been recent interest in exploring the acceleration of nonvectorizable workloads with spatially programmed architectures that are designed to efficiently exploit pipeline parallelism. Such an architecture faces two main problems: how to efficiently control each processing element (PE) in the system, and how to facilitate inter-PE communication without the overheads of traditional shared-memory coherent memory. In this article, we explore solving these problems using triggered instructions and latency-insensitive channels. Triggered instructions completely eliminate the program counter (PC) and allow programs to transition concisely between states without explicit branch instructions. Latency-insensitive channels allow efficient communication of inter-PE control information while simultaneously enabling flexible code placement and improving tolerance for variable events such as cache accesses. Together, these approaches provide a unified mechanism to avoid overserialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading. Our analysis shows that a spatial accelerator using triggered instructions and latency-insensitive channels can achieve 8 × greater area-normalized performance than a traditional general-purpose processor. Further analysis shows that triggered control reduces the number of static and dynamic instructions in the critical paths by 62% and 64%, respectively, over a PC-style baseline, increasing the performance of the spatial programming approach by 2.0 ×.

A Case Study for Comparing the Effectiveness of a Computer Simulation and a Hands-On Activity on Learning Electric Circuits

Background:Science education reform emphasizes innovative and constructivist views of science teaching and learning that promotes active learning environments, dynamic instructions, and authentic science experiments. Technology-based and hands-on instructional designs are among innovative science teaching and learning methods. Research shows that these two types of instructional methods designed with constructivist views of science are more beneficial for students in learning science concepts when compared to traditional science instruction.Materials and methods:However, the comparison of effectiveness of the two approaches as well as their affordances has not been clearly addressed. This paper presents a case study comparing the effectiveness of computer-based versus hands-on instructional activity on learning electric circuits.Results:The results show that both approaches significantly improved pre-service mathematics and science teachers’ learning of electric circuits. The two types of instructional activities did not significantly differ from each other in terms of learning gains. However, hands-on activity provided ample opportunities for group interaction as well as task-related discussions.Conclusions:This study shows that both computer-based and hands-on activities can be effective when utilized in the right classroom environment.

Reminiscences of Project Y and the ACS Project

These reminiscences relate to the period that Brian Randell spent between 1964 and 1966 first at IBM Research working on Project Y and then in the IBM Systems Development Division on the resulting ACS Project--then-secret projects that aimed to build a supercomputer that would be 100 times faster than Stretch. Randell's account is based in part on his memory, but also makes extensive use of the small set of files that he had retained, mainly relating to patent applications. A scanned copy of one of these files, the paper Dynamic Instruction Scheduling, that he coauthored with Lynn Conway, Don Rozenberg, and Don Senzig in February 1966, is available as an online Web extra https://s3.amazonaws.com/ieeecs.cdn.csdl.public/mags/an/2015/03/man2015030055s.pdf and in Newcastle University's online archive at www.cs.ncl.ac.uk/publications/trs/papers/891.pdf. Because of space constraints just the initial three pages of this paper are included in the present article, which also includes the text from a section on Interrupts that was added to the 1969 IBM San Jose Technical Report version of the 1966 paper.