Dynamic Element Matching Research Articles

An improved Random Swapping Thermometer Coding (RSTC) Dynamic Element Matching (DEM) method

ABSTRACT An improved Random Swapping Thermometer Coding (RSTC) Dynamic Element Matching (DEM) method is presented for Nyquist-rate Digital to Analog converters (DACs). In contrast to the RSTC DEM method, the presented method prevents the Spurious-free dynamic range (SFDR) reduction in DACs in low signal frequencies. Also, while ”RSTC with the restricted jumping technique” method is unable to prevent the SFDR reduction in low frequencies for non-full-scale sinusoidal signals, this new method prevents the SFDR reduction in low frequencies for both full-scale and non-full-scale sinusoidal signals. The Fast fourier transform (FFT) analysis for a behavioural model of a 6-Bit thermometer coded DAC at ( is the signal frequency and is the sample rate) shows 2.1 dB SFDR improvement in comparison to ”RSTC with the restricted jumping technique” method. In addition, the presented method achieves a reasonable trade-off between SFDR and Switching activity in comparison to other DEM methods.

A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-$\Delta\Sigma$ M Structure

This article presents a capacitively coupled voltage-controlled oscillator (VCO)-based sensor readout featuring a hybrid phase-locked loop (PLL)-ΔΣ modulator structure. It leverages phase-locking and phase-frequency detector (PFD) array to concurrently perform quantization and dynamic element matching (DEM), much-reducing hardware/power compared with the existing VCO-based readouts' counting scheme. A low-cost in-cell data-weighted averaging (DWA) scheme is presented to enable a highly linear tri-level digital-to-analog converter (DAC). Fabricated in 40-nm CMOS, the prototype readout achieves 78-dB SNDR in 10-kHz bandwidth, consuming 4.68 μW and 0.025-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area. With 172-dB Schreier figure of merit, its efficiency advances the state-of-the-art VCO-based readouts by 50×.

A Highly Linear Multi-Level SC DAC in a Power-Efficient Gm-C Continuous-Time Delta-Sigma Modulator

A highly linear multi-level switched-capacitor (SC) digital-to-analog converter (DAC) is proposed for continuous-time delta-sigma modulators (CTDSMs). A Gm-C CTDSM with a passive frontend low-pass filter (LPF) is further proposed to mitigate the problems of increased settling requirements and worsened anti-aliasing capability (consequences of an SC DAC) so as to realize an extremely power-efficient CTDSM. A 100-kHz bandwidth $40\times $ oversampling 3rd-order CTDSM prototype employing the proposed DAC and modulator topology is fabricated in a low-leakage 65-nm CMOS technology. Experimental results show that the modulator achieves a spurious-free dynamic range (SFDR), dynamic range (DR) and signal-to-noise and distortion ratio (SNDR) of 86.6 dB, 85.1 dB and 78.8 dB, respectively. To the best of our knowledge, this is the first silicon-proven CTDSM with a more-than-3-level DAC that leads to an excellent SFDR while not requiring dynamic element matching, component calibration, precise reference voltages, or an operating frequency higher than the modulator’s sampling frequency ${{f}}_{{{s}}}$ . The prototype consumes 22.8 $\mu \text{W}$ from a 1.2-V supply, amounting to a Walden’s and Schreier’s figure of merit (FoM) of 16 fJ/conv.-step and 181.5 dB, respectively, which is the best among state-of-the-art CTDSMs. It further achieves high alias rejections of 52 dB and 58 dB at ${{f}}_{{{s}}}$ and $2{{f}}_{{{s}}}$ , respectively, and can tolerate a clock period jitter of 3 ns.

A Fractional-$N$ PLL With Space–Time Averaging for Quantization Noise Reduction

This article presents a space–time averaging technique that can realize instantaneous fractional frequency division, and thus, can significantly reduce the quantization error in a fractional- $N$ phase-locked loop (PLL). Spatial averaging can be achieved by using an array of dividers running in parallel. Their different division ratios are generated by using a fractional $\Delta \Sigma $ modulator (DSM) and a dynamic element matching (DEM) block. To reduce the divider power, this article also proposes a way to achieve spatial averaging using only one divider and phase selection. A prototype 2.4-GHz fractional- $N$ PLL is implemented in a 40-nm CMOS process. Measurement results show that the proposed technique reduces the phase noise by 10 and 21 dB at the 1- and 10-MHz offset, respectively, leading to a reduction of the integrated rms jitter from 9.55 to 2.26 ps.

Delta-Sigma Modulator with Relaxed Feedback Timing for High Speed Applications

In this paper, a ΔΣ analog-to-digital converter (ADC) was designed and measured for broadband and high-resolution applications by applying the simple circuit technique to alleviate the feedback timing of input feed-forward architecture. With the proposed technique, a low-speed comparator and dynamic element matching (DEM) logic can be applied even for high-speed implementation, which helps to decrease power dissipation. Two prototypes using slightly different input branch topologies were fabricated with a 0.18 um 2-poly and 4-metal CMOS process, and measured to demonstrate the effectiveness of the proposed circuit technique. The sampling capacitor and feedback DAC capacitors were separated in prototype A, while they were shared in prototype B. The prototypes achieved 81.2 dB and 72.4 dB of SNDR in a 2.1 MHz signal band, respectively.

CMOS time-mode smart temperature sensor using programmable temperature compensation devices and $$\Delta \Sigma$$ time-to-digital converter

This work presents a time-mode smart temperature sensor in a standard 180 nm CMOS process, intended for on-chip thermal monitoring applications. A new temperature-to-pulse converter (TPC) is proposed utilising programmable temperature compensation devices, where a dual delay-line configuration is adopted, namely sensor and reference delay-lines. The proportional to absolute temperature (PTAT) delay offered by the sensor delay-line has a temperature coefficient (TC) of 720 ppm/°C, whereas almost constant delay possessed by the reference delay-line has a TC of 60 ppm/°C, over 0–100 °C temperature range. The proposed 1st-order $$\Delta \Sigma$$ time-to-digital converter (TDC) serves as the smart sensor readout, where a novel delay-cell is proposed using multipath approach. The projected $$\Delta \Sigma$$ TDC achieves 30 ns full-scale range at 9 ps resolution. The dual delay-line configuration in the TPC and the dynamic element matching in the $$\Delta \Sigma$$ TDC bound the inaccuracy of the proposed smart temperature sensor to ± 0.68 °C. The sensor shows a resolution of 0.03 °C at 0.5 $$\upmu \hbox {s}$$ conversion time.

An Untrimmed BJT-Based Temperature Sensor With Dynamic Current-Gain Compensation in 55-nm CMOS Process

This brief presents a bipolar junction transistor (BJT)-based CMOS temperature sensor without trimming. A current-mode readout scheme with dynamic current gain compensation is proposed to reduce the error caused by the low current gain $\beta $ of the substrate BJT in nanometer CMOS technologies. Combining this readout scheme with techniques, such as chopping and dynamic element matching (DEM), the sensor achieves a high untrimmed accuracy for auto-calibration in thermal management applications. Fabricated in a standard digital 55-nm CMOS process, the sensor shows a measured inaccuracy within ±1.7 °C ( $3\sigma $ ) from −40 °C to 125 °C without calibration. It occupies a die area of 0.0146 mm2 and has a power consumption of $37~\rm \mu \text{W}$ with an adjustable resolution from 12 to 15 bit and a conversion time of 4.1–32.8 ms.

Design and Analysis of a 12-b Current-Steering DAC in a 14-nm FinFET Technology for 2G/3G/4G Cellular Applications

A 14-nm FinFET CMOS 12-b current-steering digital-to-analog converter (DAC) for 2G/3G/4G cellular applications is presented herein. Bit segmentations of a 6-bit thermometer and 6-bit binary coding are adopted, utilizing switching-order shuffling in combination with dynamic element matching (DEM) to suppress the spurious tones owing to the current-source mismatch in three-dimensional FinFETs. In addition, output switches are designed to achieve make-before-break operation with the proposed low crossing point level shifter. Moreover, an output full-scale current trimming method is applied to maximize the power efficiency of the envelope-tracking (ET). The active area of a single DAC is 0.036 mm2, its power consumption is 6.1 mW, and its SFDR is 80 dBc.

A 15‐MHz bandwidth double sampling MASH25b‐15b sigma‐delta modulator with DEM for multibit DACs

SummaryA high SNDR discrete‐time (DT) 2‐1 MASH sigma‐delta modulator (SDM) for 15‐MHz bandwidth was presented. Cascade of integrators with feedforward (CIFF) scheme, combined with the optimized gain coefficients, was adopted to avoid of the integrators. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. Five‐bit flash quantizer was adopted in both stages to improve the overall signal‐to‐noise and distortion ratio (SNDR) performance, and third‐order dynamic element matching (DEM) was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated in a mature 0.18‐μm CMOS technology, the occupied area of the modulator was 0.24 mm2 and dissipation power 25.4 mW from a 1.8‐V voltage supply. As a sampling rate of 240 MHz for the input sampling and DAC and 480 MHz for the flash ADC, a SNDR of 90.2 dB over 15‐MHz signal bandwidth and the corresponding effective number of bits (ENOB) of 14.69 bit were achieved. The spurious‐free dynamic range (SFDR) was 98 dB with DEM turned on for a 3.75 MHz at −2.5‐dBFS input signal, and the figure of merit (FOM) was 30.7 fJ/conv. for 15‐MHz bandwidth. A 15‐MHz bandwidth multibit MASH2‐1 discrete‐time sigma‐delta modulator was proposed. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. High‐order DEM was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated by a 0.18‐μm CMOS process, the modulator achieved a SNDR of 90.2 dB and the corresponding ENOB 14.69 bit over 15‐MHz signal bandwidth. The proposed modulator was very suitable for wideband applications including wireless communication systems, high‐frequency biomedical imaging or sensing systems, and so on.

A CMOS temperature sensor based on duty-cycle modulation with calibration

In this paper, a digital CMOS temperature sensor based on duty-cycle modulation with digital calibration is presented. The temperature sensor generates a duty-cycle-modulated signal by applying a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current derived from substrate bipolar junction transistors (BJT) to an integrator followed by a window comparator. The duty-cycle-modulated signal is then converted to a digital representation of temperature with two counters. Calibration is performed in the digital domain with three calibration parameters. Dynamic element matching (DEM) and chopping techniques are also used to minimize the errors caused by the component mismatch. The prototype chip is fabricated in a $$0.5\,\upmu \hbox {m}$$ CMOS process. The chip area occupies $$2.3\,\hbox {mm}^2$$. Measurement results from 11 test chips show that an inaccuracy of $$-1.1{-}0.5\,^{\circ }\hbox {C}$$ is achieved over the temperature range from $$-35$$ to $$85\,^{\circ }\hbox {C}$$ after calibration. The 2.5 V supply voltage is utilized and the total power consumption is 0.83 mW at a conversion rate of 0.5 kSa/s with a resolution of $$0.0625\,^{\circ }\hbox {C/LSB}$$, leading to $$6.48-\hbox {nJ}^{\circ }\hbox {C}^2$$ resolution figure of merit (FoM) and $$2951.1-\hbox {nJ}\%^2$$ accuracy FoM.

An 8 GSps 14 bit RF DAC With IM3&lt;−62 dBc up to 3.6 GHz

This brief presents an 8 GSps 14 bit current steering RF digital-to-analog converter (DAC) for communication system. Double edge sampling method is adopted to reduce maximum clock frequency. To suppress the third-order intermodulation (IM3), current switch driver with enhanced reset circuit is proposed. An improved dynamic element matching (DEM) method based on optimized switching sequence is adopted. According to experimental result, the measured IM3 is below −62 dBc up to 3.6 GHz. The digital interpolation and up-converters block are included. Eight lane 10 Gb/s JESD 204B receiver are integrated. The chip is fabricated in 40-nm CMOS, with a die size of 2.75 ${\times }$ 3 mm2.

A 3GS/s 12-bit Current-Steering Digital-to-Analog Converter (DAC) in 55 nm CMOS Technology

A 3GS/s 12-bit current-steering digital-to-analog converter (DAC) fabricated in 55 nm complementary metal–oxide–semiconductor (CMOS) technology has been presented. A partial randomization dynamic element matching (PRDEM) method based on switching sequence optimization is proposed to mitigate the mismatch effect and suppress the harmonic distortion with low hardware complexity. In the switching current cell, the cascode structure together with “always-ON” small current sources are used to keep the output impedance high and uniform. A compact layout of the switching current array is carefully designed, featuring short wires routing and small parasitic capacitance. According to the measured results at 3GS/s, this DAC demonstrates a spurious-free dynamic range (SFDR) of 74.64 dBc at low frequency and 50 dBc at 1.5 GHz output. The chip occupies an active area of 0.2 × 0.48 mm2 and consumes a total power of 495 mW.

High Order Mismatch Shaping for Low Oversampling Rates

Delta Sigma data converters employing high order dynamic element matching (DEM) allow for accurate signal conversion in the presence of DAC mismatch. However, at low oversampling rates, current high order DEM decoders provide little or no improvement in error suppression over lower order designs. In addition, the logic requirement of the DEM decoder increases significantly with each additional DAC bit. This brief presents a high order DEM decoder that improves mismatch shaping performance at low to medium oversampling rates by up to 15 dB, while employing methods to reduce the area overhead of the vector quantizer in the design.

LW-DEM: Designing a Low Power Digital-to-Analog Converter Using Lightweight Dynamic Element Matching Technique

The need for low-power wireless sensor networks (WSNs) continues to grow. Based on the fact that digital-to-analog converters (DACs) are essential elements in the WSN and consumes a lot of power, this paper presents a new low-power DAC design to realize the low-power WSN. To do that, this paper exploits the dynamic element matching (DEM) technique, one of the well-known techniques for high performance DACs, proposes a lightweight DEM (LW-DEM) technique that minimizes power and area overhead of the DEM technique. More specifically, this paper is motivated from the observation that input data of DACs tends to be sufficiently random that the input data can be used for the random selection of the current source instead of a pseudo-random number generator (PRNG) for the traditional DEM. Because the PRNG consumes a lot of power and occupies a large area in a DAC, elimination of the PRNG from a DAC and utilizing input data result in significant power saving and area reduction in the DAC while meeting the required performance of the low-power WSNs. This paper provides a detailed LW-DEM architecture and its operation principle. To demonstrate the efficacy of the proposed method, a prototype 12-bit DAC using the LW-DEM is implemented. The 12-bit DAC is fabricated in 65 nm CMOS technology and occupies only $0.065~{mm}^{2}$ area. Measurement results with the prototype verify that the DAC using LW-DEM accomplishes 39% power saving and 52% area reduction in the randomizer, compared to a DAC using the conventional DEM. At the same time, the measured spurious-free dynamic range (SFDR) of the DAC using LW-DEM is better than 55 dB, demonstrating that the proposed DAC achieves almost same performance as a DAC using the conventional DEM.

An Automatic On-Chip Calibration Technique for Static and Dynamic DAC Error Correction in High-Speed Continuous-Time Delta-Sigma Modulators

Calibration is preferred over dynamic element matching (DEM) techniques to correct nonlinearity in digital-to-analog converters (DACs) in high-speed multi-bit continuous-time (CT) delta-sigma modulators (DSMs) to avoid introducing extra excess loop delay. The state-of-the-art calibration techniques, however, involve substantial external control, making it difficult for a complete on-chip realization. In this paper a highly automated on-chip technique for calibrating differential nonlinearity (DNL) and inter-symbolinterference (ISI) errors of a multi-bit DAC in a CTDSM is presented. The proposed technique implements a Calibration Control System (CCS), equipped with a Finite State Machine (FSM) logic, that automates the entire calibration process with minimal intervention. The calibration loop utilizes the modulator itself to produce the digital estimates of the DNL and the average ISI errors of each unit element of the DAC. These digital estimates are then used to configure auxiliary DACs for correction of the errors in the main DAC. For every unit element in the main DAC, an 8-bit dynamic auxiliary DAC injects a calibrated compensation current in the loop at every up-transition of the input data to cancel the average ISI error, and a 5-bit constant current source array corrects its DNL error. Design considerations and post-layout simulation results for a 50-MHz bandwidth, 1.8GS/s 4 th -order CTDSM are presented. The modulator has a 4.8 dB and a 10.8 dB improvement in SNDR and SFDR respectively with calibration, leading to a dynamic range of 71 dB with a total power consumption of 37.7 mW from 1.3 V and 1 V supplies.

A CT ΔΣ modulator using 4-bit asynchronous SAR quantizer and MPDWA DEM

The current paper aims at presenting a low-power second-order input-feedforward continuous-time (CT) ΔΣ modulator for audio applications. It uses a 4-bit asynchronous successive approximation register (SAR) quantizer which is more power efficient than the usual flash converter. Furthermore, in order for the proposed modulator to reduce the noise stemming from the component mismatches of the feedback digital-to-analog converter (DAC), it applies a modified partitioned data weighted averaging (MPDWA) dynamic element matching (DEM) so as to solve the DWA DEM-in band-tone problem. Despite the implementation of MPDWA, no further delay caused in the ΔΣ feedback loop compared to the conventional DWA. The implementation of the above-mentioned DEM in the modulator and required reforms have led to a new design with better performance and favorable figure of merit (FOM) value. The designed modulator which is simulated using 0.18 µm CMOS technology, achieves 84.17 dB SNDR for 20 kHz signal bandwidth and dissipates 54 µW while its FOM is obtained about 143 fJ/conv.-step.

A resistive DAC for a multi-stage sigma-delta modulator DAC with dynamic element matching

This paper presents a study and implementation of a shunt–shunt resistive voltage divider digital-to-analog converter (DAC) for use as a multibit DAC in a multi-stage noise shaping sigma-delta modulator DAC design with dynamic element matching. This resistive DAC structure is employed to address the problem of code-dependent finite output impedance and thus aims to improve systematic linearity, while still being suitable for scaled CMOS processes. Chip measurement results from an implementation in CMOS 180 nm technology are presented. At low sampling clock frequencies, an SFDR of 71.81 dB is achieved, while at a higher sampling clock frequency of 600 MHz the SFDR is measured to be 59.73 dB, all for an OSR of 32. Our results show that low systematic nonlinearity can be achieved with this resistive DAC at low sampling frequencies, and we discuss potential enhancements to our prototype to obtain better SFDR at higher sampling rate.

Power-Scalable Dynamic Element Matching for a 3.4-GHz 9-bit $\Delta\Sigma$ RF-DAC in 16-nm FinFET

This letter presents a hardware-efficient technique to scale the power consumption of dynamic element matching (DEM) DACs with the static back-off level of the digital input signal. Unlike previous DEM techniques, the proposed power-scalable approach disables parts of the DEM encoder and DAC elements when the digital signal level is decreased from full-scale, thus resulting in reduced power consumption and lower mismatch noise at the DAC output. Power-scalable DEM is particularly useful in digital-intensive RF transmitters, where 30–50 dB of signal power control may be performed in the digital domain. The concept is demonstrated for a 3.4-GHz 9-bit I/Q RF-DAC, utilizing bandpass delta–sigma modulation and DEM with programmable center frequency. The circuit is fabricated in a 16-nm FinFET process. When changing the digital back-off level of an LTE20 carrier from 0 to −18 dB, measurement results show a 72% reduction in total power consumption and 4.5-dB lower mismatch noise, achieved without performing any bias tuning or gain control in the analog domain. The digital delta–sigma modulator and DEM encoder consume less than 20 mW in full-scale mode.

High Dynamic Performance Current-Steering DAC Design With Nested-Segment Structure

Dynamic performance of the current-steering digital-to-analog converter (DAC) is mainly affected by the mismatch-induced nonlinearity. Dynamic-element-matching (DEM) method has been widely employed to effectively improve the amplitude and timing mismatches. However, the maximum performance improvement is constrained by the conventional separate-segment structure for the current source array. In this brief, a DEM DAC with nested-segment structure is proposed to improve the mismatch performance. Compared with the best spurious-free dynamic range (SFDR) values obtained by the conventional DEM DACs, Monte Carlo simulations demonstrate that the proposed DAC achieves higher performance improvement with the same MSB bit width. The largest improvement occurs at MSB bit width of 3 with the 6.95- and 4.68-dB gain over two conventional designs, respectively. In terms of the digital complexity, the proposed architecture employs at least $2.7\times$ fewer multiplexers compared with the reported DEM DACs, while achieving comparable dynamic performance. Fabricated in 130-nm CMOS process, the proposed 12-bit 100-MS/s DAC occupies 0.21 mm2. Measurement results show that $1.9\times$ integral nonlinearity reduction ratio and 15.5-dB SFDR improvement from 46.6 to 62.1 dB at near Nyquist frequency are achieved.

Two-Dimensional Structure Compatible with DEM Methods Utilizing in DACs

A two-dimensional digital-to-analog converter (DAC) structure compatible with dynamic element matching (DEM) methods is presented. Unlike the DACs using segmented structure for employing DEM, the new structure randomizes inter-segment error. This advantage is achieved because of the characteristics of the algorithm of two-dimensional decoding. The simulation results in 180[Formula: see text]nm CMOS technology, 319.72[Formula: see text]MHz signal frequency and 800[Formula: see text]MS/s sample rate for an 8-bit two-dimensional DAC utilizing the presented structure, shows 14.94[Formula: see text]dB spurious-free dynamic range (SFDR) improvement compared to the SFDR of the same DAC without employing the presented structure. Also, the IMD3 of the DAC employing the presented structure for [Formula: see text][Formula: see text]MHz and [Formula: see text][Formula: see text]MHz is 50.1[Formula: see text]dB.