High Dynamic Performance Current-Steering DAC Design With Nested-Segment Structure

Abstract

Dynamic performance of the current-steering digital-to-analog converter (DAC) is mainly affected by the mismatch-induced nonlinearity. Dynamic-element-matching (DEM) method has been widely employed to effectively improve the amplitude and timing mismatches. However, the maximum performance improvement is constrained by the conventional separate-segment structure for the current source array. In this brief, a DEM DAC with nested-segment structure is proposed to improve the mismatch performance. Compared with the best spurious-free dynamic range (SFDR) values obtained by the conventional DEM DACs, Monte Carlo simulations demonstrate that the proposed DAC achieves higher performance improvement with the same MSB bit width. The largest improvement occurs at MSB bit width of 3 with the 6.95- and 4.68-dB gain over two conventional designs, respectively. In terms of the digital complexity, the proposed architecture employs at least $2.7\times$ fewer multiplexers compared with the reported DEM DACs, while achieving comparable dynamic performance. Fabricated in 130-nm CMOS process, the proposed 12-bit 100-MS/s DAC occupies 0.21 mm2. Measurement results show that $1.9\times$ integral nonlinearity reduction ratio and 15.5-dB SFDR improvement from 46.6 to 62.1 dB at near Nyquist frequency are achieved.