Dynamic Avalanche Research Articles

A Dynamic Self-Clamping Caused by Dynamic Avalanche During the Turn-Off of PT-IGBT

A dynamic self-clamping is found during overstress turn-off of the PT-insulated gate bipolar transistor (IGBT) with a higher carrier lifetime. Theoretical analysis and numerical device simulation reveal that it is caused by the remaining plasma that cannot be completely removed due to dynamic avalanche injection. A 1-D physics-based analytical model for the self-clamping is established, and analytical results indicate that clamped voltage is inversely proportional to the initial turn-off current density and the carrier lifetime. When the dc-link voltage is larger than the clamped voltage of the device at a certain turn-off current, both terminal voltage and terminal current will be clamped, causing the device to lose control of the gate. Simulations of the multicell structure demonstrate that the avalanche-generated current filament under the self-clamping is stationary and may exist for a longer time, which is extremely likely to lead to local overheat and device destruction.

Analytical model for dynamic avalanche onset of planar IGBTs

Dynamic avalanche effect can occur due to the influence of free carrier on electric filed during inductive turn-off of IGBT, which is a critical factor influencing the device reliability. In this paper, a one-dimensional (1-D) analytical model for dynamic avalanche onset is at first derived based on the basic principles of semiconductor and it gives insight into the details of internal physical mechanisms of the device at the onset of dynamic avalanche. Then the critical structural parameters affecting the onset of dynamic avalanche are examined. By introducing a modification factor K into the 1-D model, a rough two-dimensional (2-D) analytical model that can reflect nonuniformity of the current distribution qualitatively during the turn-off of planar IGBTs is eventually obtained.

Evaluation of Dynamic Avalanche Performance in 1.2-kV MOS-Bipolar Devices

It is well-known that the dynamic avalanche (DA) phenomenon poses fundamental limits on the power density, turn-off power loss, dV / dt controllability, and long-term reliability of MOS-bipolar devices. Therefore, overcoming this phenomenon is essential to improve the energy efficiency and ensure their safe operation. In this work, a detailed analysis of the 1.2-kV MOS-bipolar devices is undertaken through both calibrated TCAD simulations and experiments to show the fundamental cause of DA and the impact of the current density, supply voltage, and 3-D scaling rules on the DA performance. Furthermore, the DA performance of a 1.2-kV non-punch-through (NPT) trench clustered insulated gate bipolar transistor (TCIGBT) is evaluated for high current density and low power loss operations. The results indicate that this device configuration is free of DA and can be used for ultrahigh current density operation in an energy-efficient manner.

Turn-OFF dV/dt Controllability in 1.2-kV MOS-Bipolar Devices

Turn- off dV/dt controllability is an essential feature in insulated gate bipolar transistors (IGBTs) for flexible design in power switching applications. However, the occurrence of dynamic avalanche (DA) during the turn- off transients plays a key role on the turn- off power loss, dV/dt controllability and safe operating area of IGBTs. This article aims to clarify the impact of DA on the turn- off characteristics of 1.2-kV trench IGBTs through three-dimensional technology computer aided design (TCAD) simulations as well as experimental demonstrations. Measurement results show that DA is enhanced at high current density and high supply voltage conditions, which aggravates its influence on the dV/dt controllability as well as turn- off power loss. To eliminate the DA for high current density and low loss operations, a DA free design is experimentally demonstrated in the Trench Clustered IGBT (TCIGBT). Due to effective management of electric field and unique p-channel metal oxide semiconductor (PMOS) actions during turn- off, TCIGBT can retain high dV/dt controllability and low power loss at high current density operations.

Introduction of the energy to break an avalanche as a promising parameter for powder flowability prediction

Dynamic avalanche testing is a newer method useful even with cohesive powder samples. To evaluate flow properties of pharmaceutical powder excipients, break energy (BE) is introduced as a new promising avalanche parameter. Conventional pharmacopoeial methods and an annular shear cell were utilized to characterize 23 pharmaceutical powder samples including binary mixtures. Subsequently, rotating drum avalanching was studied to better understand behaviour of powders. A good linear regression between the energy to break a powder avalanche and powder cohesion with R2 = 0.823 was detected. The relationship between BE and the flow function value, estimated by shear testing, allowed to identify two samples with excellent flow functions: Cellets 100 and Neusilin US2. The latter sample also had very low BE although the mass flow rate was the poorest observed out of 23 samples. Therefore, the BE from avalanching testing seems to be a sensitive measure of cohesion and flow function behaviour.

Alternated Trench-Gate IGBT for Low Loss and Suppressing Negative Gate Capacitance

A new gate structure in the trench-gate insulated-gate bipolar transistor (IGBT) design is proposed and analyzed for power-loss reduction and the suppression of electromagnetic-interference (EMI) noise. Although the turn-off loss and the ON-state voltage drop ${V}_{\text {ce(sat)}}$ are improved by the injection-enhancement (IE) effect, the IE effect caused dynamic avalanche that limits the turn-off loss reduction. In addition, EMI noise is induced by high dI / dt and large surge current due to the negative gate capacitance. This article shows that the dynamic avalanche and the negative gate capacitance can be suppressed by the management of the electric field concentration and hole current flow around the trench gate by the proposed alternated trench-gate (AT) IGBT structure, and both low power loss and good switching controllability can be obtained. The device simulation results show that the AT-IGBT improves the turn-on surge current ${I}_{\text {surge}} - {V}_{\text {ce(sat)}}$ tradeoff compared with the conventional IGBTs.

Surface Buffer IGBT for High Total Performance

A new structure in trench-gate insulated gate bipolar transistor (IGBT) design is proposed and analyzed not only for power loss reduction but also for long-term stability and suppressing electromagnetic interference (EMI) noise using a device simulation. Although turn-off loss and ON-state voltage drop ${V}_{\text {ce(sat)}}$ are improved by injection enhancement (IE) effect, IE effect causes dynamic avalanche that limits turn-off loss reduction and degrades long-term stability by the charge trap at the trench gate oxide interface. In addition, hole current around the gate induces EMI noise due to the negative gate capacitance. This article shows that the proposed surface buffer (SB) IGBT suppresses dynamic avalanche and negative gate capacitance maintaining low power loss by covering the trench gate bottom and hole evacuation from the pMOS channel.

Investigation on 4H-SiC gate turn-off thyristor with direct carrier extraction access to drift region for power conversion applications

4H-SiC gate turn-off (GTO) thyristor offers extraordinary advantages over its counterparts in handling ultra-high voltage electric power conversion applications because of its relatively low forward voltage drop at high conduction current density. Besides, though the SiC thyristors never suffer from long carrier liftime induced large switching loss like Si thyristors, the peak temperature rise rather than dynamic avalanche breakdown is blamed for the safe operation area (SOA) failure, making further reduction of power loss in SiC GTOs even more important. In this paper, a 20 kV SiC GTO with direct carrier extraction access to its drift region (DA-GTO) is investigated to explore the benefit this structure could bring for SiC thyristors, namely achieving smaller switching loss and/or potential larger SOA with slight sacrifice in forward voltage drop at high current. The structure is formed by interleaved P+ ion implantation into part of the thin N-injector layer based on conventional 20 kV SiC GTO. The SiC DA-GTO operates in BJT mode at low current, and in GTO mode with low forward voltage drop at high current. During turn-off process, it offers a direct current path to quickly sweep out the excess carriers in the P-drift region, thus speeds up the turn-off process and decreases the turn-off loss. Simulation results show that its turn-off loss reduces by 37.4%, contributing to 12.6% reduction in total power loss, compared with SiC GTO. Therefore, SiC DA-GTO is a very promising choice for next-generation power conversion systems.

Analysis of OFF-state dynamic avalanche instability in silicon-on-insulator lateral IGBTs at low temperature

The dynamic avalanche instability in the silicon-on-insulator (SOI) lateral insulated-gate bipolar transistors (LIGBT) at low temperature is investigated. The measured results show a time-dependent collector-emitter voltage (VCE) walk event at –40 °C under the OFF-state dynamic avalanche conditions. A charge couple is proposed and TCAD simulations are performed for the mechanism revealing. It is found that the dynamic avalanche instability is closely related to the hole accumulation at the collector-side bottom, the depletion in P-type substrate (P-sub) and the transfer of the breakdown spot. The optimization strategy for the dynamic avalanche stability is drawn based on the revealed mechanism. The VCE walk can be suppressed or eliminated by preventing the dynamic expansion/shrinking behaviour of the depletion layer in substrate or satisfying an equal relationship between the vertical breakdown voltage (BVV) and the lateral breakdown voltage (BVL). With different device types, collector structures, N-drift lengths, BOX thicknesses, substrate biases and substrate types, the VCE walk events at low temperature (–40 °C) are comprehensively discussed in this paper. The VCE walk can be completely eliminated through replacing the P-sub by the N-type substrate (N-sub).

On the development of powder spreadability metrics and feedstock requirements for powder bed fusion additive manufacturing

Existing powder feedstock metrics for powder bed fusion (PBF) additive manufacturing (AM) are related to packing efficiency and flowability, and newer techniques, such as powder rheometry and dynamic avalanche testing, have received recent attention in the literature. To date, however, no powder characterization technique is able to predict the spreadability of AM feedstock. In fact, no such spreadability metrics exist. This study endeavored to establish viable powder spreadability metrics through the development of a spreadability testing rig that emulates the recoating conditions present in commercial PBF AM systems. As no metrics for spreadability currently exist, four potential metrics were evaluated in a 3∙23 split plot experimental design. These four metrics were: (1) the percentage of the build plate covered by spread powder, (2) the rate of powder deposition, (3) the average avalanching angle of the powder, and (4) the rate of change of the avalanching angle. Three samples of gas atomized, Al-10Si-0.5 Mg PBF powder representing differing degrees of quality were used as the levels of the powder quality input variable. As no powder quality metrics have been shown to be indicative of powder spreadability in PBF, various bulk powder characteristics were used as the powder quality indicator during ANOVA. Of the four metrics tested, the average avalanching angle, while statistically dependent of the powders angle of repose, showed poor correlation with experimental data. The remaining three metrics, however, were all found to have a statistically significant dependence on the angle of repose. Increasing the angle of repose resulted in significantly worse powder spreading, i.e. poor build plate coverage and powder clumping, as measured by the viable spreading metrics. Other processing parameters, such as the recoating speed and the recoater blade material were shown to also influence the spread quality.

Inhibition of peak electric field shifting on current filaments of high voltage diode

The buffer layers can improve significantly the ruggedness of a high voltage diode, but the inhibition mechanism on current filaments is unclear. In this paper, an analysis of the electric field gradient analytical model is used to explain the peak electric field shifting of high voltage diode with buffer layers during reverse recovery, and the influence of the buffer layers on current filament during reverse recovery is analyzed. Electrothermal simulations show that the peak electric field shifting even occurs before dynamic avalanche, leading to the appearance of the positive differential resistance. A self-stabilizing mechanism that the increase of the electric field strength in buffer layers is restrained after the peak electric field shifting is found. This provokes the weak dynamic avalanche inside high voltage diode, and the current filaments are inhibited.

Geo-spatial Modeling for Automated Demarcation of Snow Avalanche Hazard Areas Using Landsat-8 Satellite Images and In Situ Data

The aim of this study is to generate a reliable dynamic snow avalanche hazard map using analytical hierarchy process method based on multisource geo-spatial data for the Chowkibal–Tangdhar (C–T) road axis in Jammu and Kashmir (J&K), India. Avalanche-prone areas of C–T axis have been demarcated using three causative parameters, i.e., terrain, ground cover and meteorological parameters. Terrain parameters, e.g., elevation, slope, aspect and curvature, have been estimated from Advanced Spaceborne Thermal Emission and Reflection Radiometer, Global Digital Elevation Model Version 2. Ground cover information has been extracted from Landsat-8 data. Meteorological parameters maps, i.e., snow depth, relative humidity and air temperature, have been generated using geo-spatial interpolation techniques of in situ data. All the parameters have been incorporated in Geographic Information System environment to generate the hazard map. Validation of hazard map was accomplished with the area under the curve method. The prediction rate was observed to be 93.2%. Further, 20% of the study area was estimated having no hazard, 55% as low hazard, 12% as moderate hazard and 13% as high hazard on April 13, 2015. Dynamic hazard map thus generated using remote sensing and in situ data will be useful for mitigation of snow avalanche hazard, regional planning for development of infrastructure, transportation, troops movement, army deployments and communication network.

Study on the destruction mechanism caused by dynamic avalanche in GCTs

Dynamic avalanche is one key factor limiting the safe operating area (SOA) of the gate commutated thyristors (GCTs). The current filament caused by dynamic avalanche and its failure mechanism still need to be studied in depth. In this paper, the relevant theoretical analysis and device simulations are firstly carried out. And a 2-D model describing quantitatively the plasma front velocity is derived to examine the behaviour of the filament. The results show that the avalanche effect at the pn- junction and the hole injection of p-anode region in the GCT can interact with each other during the turn-off, but it does not necessarily lead to the device destruction. However, when the GCT is turned off at high dc-link voltage, the interaction transforms into a positive feedback effect, and the anode-cathode voltage is clamped to a certain value, resulting in the formation of destructive filament. Additionally, the borderline limited by the voltage clamping is given.

SJ-MOSFET with wave-type field limiting ring for high di/dt robustness of body diode reverse recovery

In this letter, a novel Superjunction Metal-Oxide -Semiconductor Field Effect Transistor with wave-type field limiting ring (WFLR-SJ-MOSFET) is proposed to improve the di/dt robustness of body diode reverse recovery. When SJ-MOSFET body diode goes through reverse recovery, the WFLR can suppress and rebuild the peak electric field which is resulted from the large current flowing through the sensitive terminal boundary region. As a consequence, the ruggedness of dynamic avalanche during reverse recovery is optimized. Finally, the di/dt robustness of WFLR-SJ-MOSFET body diode reverse recovery is improved by 3.2 times from 72 A/μs to 320 A/μs comparing with the conventional SJ-MOSFET.

Fast Ionization-Front-Induced Anomalous Switching Behavior in Trigger Bipolar Transistors of Marx-Bank Circuits Under Base-Drive Conditions

The operation of transistorized Marx-bank circuits (MBCs) is analyzed, and physics-based modeling is used to understand the anomalous switching behavior of the first stage single trigger avalanche transistors of MBCs at high-current-injection conditions. The role of a voltage trigger pulse having variable rise time when applied to the base terminal is investigated to model the underlying physics of the anomalous switching behavior. Experimental observations related to ultrafast anomalous switching mechanisms of trigger transistor, i.e., either primary breakdown or current mode secondary breakdown, for faster and slower base drives are presented. This demonstrates the importance of the dynamic avalanche process and reverse saturation current on the switching mechanism under high-speed base-trigger ramps for different avalanche BJTs from various manufacturers and different lots. The agreement between 2-D TCAD device simulation results and the experimental observations shows the validity of the proposed theory when the base width and mobile carrier recombination rate are used as parameters in the device simulation setup.

Dinamik Çığ Tehlike Değerlendirmesi İçin Bayes Ağlarının CBS'ye Entegrasyonu: UKVA Perspektifi

Natural hazard assessments are core to risk definition and early warning systems and play a fundamental role in the prevention of major damages. Traditional hazard identification methods are static. For this reason, new information and conditions cannot be easily included in the pre-defined hazard assessments. The Bayesian Networks can be used effectively for dynamic hazard identification. In this study, a methodology based on the Bayesian Networks model is presented for dynamic avalanche hazard assessment, in which changed and renewed data can be included in the system. In the proposed methodology, the integration of the Bayesian Networks and Geographical Information Systems (GIS) is modeled in the National Spatial Data Infrastructure (NSDI) perspective. In this structure, it is possible to combine and analyze the data obtained from different sources and factors for avalanche hazard can be dynamically updated with real-time updated data and temporal hazard mapping can be produced. The proposed methodology provides a generic structure and has an attribute making it applicable for dynamic mapping studies for other disasters.

Analysis of integrated thyristor switching-off by a reverse gate pulse current

To increase the maximum power current density of an integrated n+p'Nn'p+-type thyristor during switching-off by a current pulse in the control circuit, the injection of electrons from the n+ emitter should be interrupted before the recovery of the collector p'N junction. This has been done using a rapidly increasing reverse gate current pulse with an amplitude equal to the amplitude of the power switched-off current. After the interruption of the emitter injection, the remaining current through the device is the current of holes extracted from the collector region via the gate electrode. Like in insulated gate bipolar transistors (IGBTs), the physical mechanism that limits the maximum density of the switch-off current is the dynamic avalanche breakdown, which is initiated by the holes extracted through the space charge region of the collector p'N junctions.

Extraction of dynamic avalanche during IGBT turn off

When IGBTs are switched with high dV/dt at high currents, dynamic avalanche occurs. Under certain conditions, this phenomenon is known to potentially degrade certain IGBT architectures. An investigation of the possible degradation of our planar IGBTs was started. This paper presents a method to extract the current (and consequently charge and energy) due to dynamic avalanche from measured turn off waveforms. The method is checked with TCAD simulations and applied to an accelerated stress test on two different device designs.

Influence of carrier lifetime distribution on the current filament in high voltage diode

The current filament caused by strong dynamic avalanche during reverse recovery of a high voltage diode under extreme overstress conditions is an important factor of the device failure. The influence of carrier lifetime distribution on the current filament during reverse recovery of the high voltage diode was analyzed by the comparison between the uniform carrier lifetime distribution and the local low carrier lifetime distributions, and the variation process and the inhibition mechanism of the current filaments in diode were discussed. Electrothermal simulations show, how the local low carrier lifetime distributions can provoke the evolution of the anode-side current filaments and the appearance of multiple cathode-side current filaments. It is deduced that the low on-state plasma at the anode side is supposed to be the essential reason for the inhibition of the current filaments.

Dynamic properties of diamond high voltage p–i–n diodes

The switching characteristics of a diamond p+–i–n+ diode have been investigated to highlight the reverse recovery phenomenon, which is a consequence of the base conductivity modulation. The electrical transport within a diamond p+–i–n+ diode is still unclear, and the effectiveness of the base conductivity modulation remains the main concern. The measured turn-off waveforms of the diamond p+–i–n+ diode showed reverse recovery, thus confirming its bipolar nature. The diamond p+–i–n+ diode exhibits soft recovery and very fast switching behaviors (the recovery time was less than 200 ns). Moreover, according to the switching conditions, the reverse recovery in the diamond p+–i–n+ diode may induce a turn-off failure, which is ascribed to the well-known dynamic avalanche breakdown.