Abstract
The dynamic avalanche instability in the silicon-on-insulator (SOI) lateral insulated-gate bipolar transistors (LIGBT) at low temperature is investigated. The measured results show a time-dependent collector-emitter voltage (VCE) walk event at –40 °C under the OFF-state dynamic avalanche conditions. A charge couple is proposed and TCAD simulations are performed for the mechanism revealing. It is found that the dynamic avalanche instability is closely related to the hole accumulation at the collector-side bottom, the depletion in P-type substrate (P-sub) and the transfer of the breakdown spot. The optimization strategy for the dynamic avalanche stability is drawn based on the revealed mechanism. The VCE walk can be suppressed or eliminated by preventing the dynamic expansion/shrinking behaviour of the depletion layer in substrate or satisfying an equal relationship between the vertical breakdown voltage (BVV) and the lateral breakdown voltage (BVL). With different device types, collector structures, N-drift lengths, BOX thicknesses, substrate biases and substrate types, the VCE walk events at low temperature (–40 °C) are comprehensively discussed in this paper. The VCE walk can be completely eliminated through replacing the P-sub by the N-type substrate (N-sub).
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