Duty Cycle Corrector Research Articles

A 65-nm duty-cycle corrector achieving 10% to 90% duty-correction range with [formula omitted]0.86% duty-cycle error

This brief introduces a dual-loop analog duty-cycle corrector (DCC) designed to enhance the in-band phase noise performance of phase-locked loops (PLLs) by achieving precise duty cycle correction over a wide input duty cycle range. The proposed DCC incorporates a duty-cycle adjustor (DCA) within each loop, working in conjunction with a low-pass filter (LPF) and a duty-control amplifier to regulate the feedback control voltage. The feedback control voltage within each loop fine-tunes the timing delay of input pulse, ensuring that the output duty cycle of each loop is adjusted to 50%. Consequently, the proposed DCC demonstrates an expanded duty correction range. The proposed DCC was fabricated in a 65-nm standard CMOS process with an active area of 0.078 mm2. Measurement results validate the efficiency of the proposed DCC in correcting a wide range of input duty cycles (i.e., 10% to 90%) to an output duty cycle of 50% with a maximum duty cycle error of <0.86% for an input clock frequency ranging from 1 MHz to 100 MHz. To further showcase its effectiveness, the duty-corrected clock was supplied to a commercially available PLL (ADF4351). This demonstrated a noteworthy reduction of approximately 19 dB in reference spurs and a 10 dBc/Hz in the in-band phase noise.

A shared TDC-based fast-lock all-digital DLL using a DCC-embedded delay line

A novel shared time-to-digital converter (TDC)-based, fast-locking, all-digital delay-locked loop (DLL) incorporating a duty-cycle corrector (DCC)-embedded delay line is introduced. The proposed DLL employs a shared TDC-based structure for both phase locking and duty-cycle correction operations, enabling rapid lock times of approximately 22 clock cycles. The proposed DLL offers the benefit of resolving the delay mismatch issue and achieving a rapid lock time by utilizing a shared delay line structure for both the TDC and the DCC-embedded delay line. This approach allows for high-speed operation up to 3.5 GHz. Implemented using a 65-nm 1.0-V CMOS process, the proposed DLL supports a frequency range from 0.8 to 3.5 GHz, offers a duty-cycle correction range of ±20 % at 0.8 GHz. It achieves an effective peak-to-peak output clock jitter of just 5.4 ps at 3.5 GHz, while maintaining a compact active area of 0.08 mm2 and operating with a power consumption of only 8.0 mW at 3.5 GHz.

Programmable delay line with inherent duty cycle correction

In the recent HBM2E IO design, clock is transmitted differentially to the external DRAM and duty cycle distortion (DCD) could add to the differential clock due to traversing multiple stages in DRAM. At higher data rates, the DCD from the differential clock imposes restrictions on the timing margins. In the current work, Tx clock path is added with DCC feature to compensate for any DCD errors introduced by the clock network in the external DRAM. Linearity of the DCC is critical metric when the clock is differential and running at high speed. A new programmable delay line with inherent DCC design with good linearity is presented in this paper.

A wide-frequency all-digital duty cycle corrector with self-adaptive configurable delay chain

A wide-frequency all-digital duty cycle corrector with self-adaptive configurable delay chain

Digital duty-cycle correction circuit for clock paths in radiation-tolerant high-speed wireline transmitters

Ongoing developments in the field of radiation-toleranthigh-speed transmitters (HSTs)aim at increasing the data rates above 25 Gb/s while increasingtotal ionizing dose (TID)tolerance above 1 Grad. The use of half-rate architectures imposes tight constraints on clock signal quality, in particular its duty-cycle. Radiation degradation of transistors in the clock path causesduty cycle distortion (DCD), affecting the output signal quality of the HST. In this paper, a digitally controlled duty-cycle correction circuit suitable for HST is presented. It compensates forprocess voltage temperature (PVT)variations as well as radiation-induced duty-cycle distortion of the clock.

Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI

A low-power delay-locked loop (DLL)-based frequency multiplier is presented. The multiplier is designed in 22 nm FDSOI and achieves 8× multiplication. The proposed DLL uses a new simple duty cycle correction circuit and is XOR logic-based for frequency multiplication. Current starved delay cells are used to make the circuit power efficient. The circuit uses three 2× stages instead of an edge combiner to achieve 8× multiplication, thus requiring far less power and chip area as compared to conventional phase-locked loop (PLL) circuits. The proposed 8× multiplier occupies an active area of 0.09 mm2. The measurement result shows ultra-low power consumption of 130 µW at 0.8 V supply. The post-layout simulation shows a timing jitter of 24 ps (pk-pk) at 2.44 GHz.

An all-digital built-in-self-test scheme for duty cycle corrector with de-skew circuit in NAND Flash memory

This paper presents an all-digital built-in-self-test (BIST) scheme to quickly test the duty cycle corrector (DCC) with de-skew circuit in NAND Flash memory. The proposed BIST circuit adopts an adjustable duty cycle module to generate the input signal of DCC, then it utilizes a high-resolution vernier time-to-digital converter to quantify the pulse widths related to duty cycle and phase difference into digital codes. The proposed BIST scheme can quickly obtain accurate measurement results of the input/output duty cycle of DCC and the phase difference of signals without using high-precision test equipment, it is a low-cost built-in testing solution for NAND Flash memory. The test chip is fabricated using 130 nm CMOS process. The area occupies 0.0425 mm2, and the proposed circuit consumes 2 mW when supply voltage is 1.2 V and clock frequency is 1 GHz. The experimental results show that the measurement error of duty cycle is in the range of −0.85% to 1.5% and the measurement error of phase difference is within ±6 ps.

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

SummaryThis paper proposes a wireline serial link transceiver for on‐package die‐to‐die links based on 12‐nm fin field‐effect transistor (FinFET) technology. The link is crucial for improving the computational performance of larger systems built from chiplets. To achieve high pin/energy efficiency and prevent traditional single‐ended signaling disadvantages, the transceiver adopts single‐ended ground‐reference signaling (GRS) to transfer information. To precompensate for the frequency‐dependent loss, retain the advantages of GRS, and avoid the disadvantages of traditional AC‐coupled equalizer, the transmitter in the transceiver adopts a DC‐coupled switched‐capacitor charge pump equalizer that can transmit GRS and its equilibrium value can be adjusted according to the channel attenuation. This paper proposes a method for timing de‐skew using digital control delay lines to eliminate the timing skew between data and the clock. In addition, this paper presents a duty cycle corrector to avoid duty cycle distortion, with an adjustment range of 44.5% to 52% and a power dissipation of only 30 W. The transceiver has an area of 1.016 0.676 mm2, including one clock lane link and four data lane links. At a nominal 0.8‐V power supply voltage, the aggregate eye‐opening of the measured 25 Gb/s data on an organic substrate channel with an attenuation of −2.2 dB over 6 mm is 0.675 UI, with a bit error rate (BER) of less than 10−12 and an energy efficiency of 1.01 pJ/bit.

A 208-MHz, 0.75-mW Self-Calibrated Reference Frequency Quadrupler for a 2-GHz Fractional-N Ring-PLL in 4-nm FinFET CMOS

This paper presents a 208-MHz, 0.75-mW selfcalibrated reference frequency quadrupler (RFQ), which provides a 4x higher reference clock with minimal deterministic frequency error. The digital-assisted calibration technique is exploited to compensate wide range of frequency and duty cycle errors and to reduce the noise degradation of analog calibration loop. Also, instead of utilizing a duty cycle corrector for 2x clock, reusing a delay cell reduces the power consumption by 50%. The fractional-N ring-PLL with the proposed RFQ was implemented in a 4nm FinFET CMOS process. The active area of the RFQ is 0.0175mm2 while the whole PLL occupies the area of 0.109mm2. By using the RFQ, the measured RMS-jitter of the PLL is definitely improved from 6.6ps to 3.35ps at 1.92GHz output frequency.

A 3–5 GHz, 108fs-RMS jitter, clock receiver circuit for time-interleaved ADCs with a sampling rate of 4 GS/s

This paper presents a high-speed, low-jitter, and high-precision clock receiver circuit (CLKRX) for time-interleaved ADCs with a sampling rate of 4 GS/s operating in the 3–5 GHz frequency range. The CLKRX circuit is composed of a continuous-time linear equalizer (CTLE) and a duty-cycle corrector (DCC). The CTLE featuring active feedback, negative Miller capacitance, and source-follower feedback is capable of enhancing the bandwidth, and improving the quality of the high-speed clock. Whereas the 3–5 GHz DCC module contains a common-mode voltage correction circuit and a wideband amplifier that corrects the input signal's duty cycle ranging from 20% to 80%. A second-order duty-cycle detection circuit is used in the feedback loop, which significantly improves the range and accuracy of duty-cycle correction and greatly reduces duty cycle jitter.The clock receiver circuit proposed in this paper was verified in a 28 nm CMOS process, and the test results show that the output duty cycle is corrected to 50 ± 0.1% within the input duty cycle range of 20–80% (3–5 GHz).

A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted a dual delay line structure, each delay line was composed of a coarse adjustment and a fine adjustment unit, and the dual delay lines had corresponding control units to reduce the mismatch between the delay lines, and it avoided the complicated design of duty cycle correction (DCC) circuit. A frequency divider was added to divide the input clock to achieve a wider input clock duty cycle adjustment. Additionally, a simple clock synthesis circuit was proposed to synthesize the required clock. The DLL design used the 25 nm process with a voltage of 1.2 V. The simulation results showed that at a working frequency of 1.6 GHz, the peak-to-peak jitter of the DC-DL DLL after locking was approximately 17.61 ps, the maximum output duty cycle error was about 1.3%, and the input duty cycle ranged from 20% to 80%, with a power consumption of 10.06 mW.

A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit

AbstractThis paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz.

A DTC-based Fractional-N DPLL using probability-density-shaping spur immunity and Q-noise reduction techniques for IoT applications

A Digital-to-Time Converter based (DTC-based) fractional-N digital phase-locked loop (DPLL) using probability-density-shaping (PDS) spur immunity and quantization phase (Q-noise) reduction techniques is presented. PDS-DSM is used to generate a loop spur immunity control code for DTC. A diff type dither is proposed to further suppress the fractional spur. The loop nonlinearity will not cause fractional spurs if certain conditions are obeyed. Moreover, to reduce the quantization noise, a configurable Phase Interpolator (PI) with 0.125/0.25/0.5/1.0 division step is integrated with a multi-module divider (MMDIV), leading to an 18-dB Q-noise suppression. A reference doubler with duty-cycle correction is adopted to further reduce phase noise. The fractional spurs are greatly mitigated by combining the PDS-DSM and phase interpolator. A DPLL prototype using the aforementioned techniques was designed in a 40-nm standard CMOS process, occupying a 0.99 mm2 silicon area. At a near-integer-N frequency, i.e., near 2.23 GHz, with PDS turned on and off, the post-layout simulated fractional spur is −59 dBc and −20 dBc, respectively. The RMS jitter of the whole chip is 4.218 ps, corresponding to a figure of merit (FOM) of −220.5 dB.

A duty cycle corrector with dual loop low pass filter for low jitter and fast correction time

In this paper, a duty cycle corrector (DCC) with a dual loop low pass filter (DLLPF) has been proposed to improve correction time and noise characteristics. It shows that the correction time is 4.25 times faster and the fluctuation is 7.86 times lower compared to a conventional DCC with a typical low pass filter. The proposed DCC has been fabricated in a 0.18-μm CMOS technology with a supply voltage of 1.8 V within area of 0.03 mm2. The experimental results show that the operation range is from 800 MHz to 1.6 GHz for input duty cycle variation within 25 % and 75 %. At the 1.6 GHz operating frequency, the measured root-mean-square and peak-to-peak jitters are 1.66 ps and 12.69 ps, respectively.

Design of duty cycle correction circuit using ASIC implementation for high speed communication

This research proposed an accurate Duty Cycle Correction (DCC) circuit for high-frequency systems with high measurement accuracy. It is a crucial component of Very Large Scale Integration (VLSI) circuits and is applied as a percentage of the measured average power of a modulated signal to obtain the signal power. This circuit uses two stages of correction, with the first stage performing course correction and the second stage performing fine corrections. This allows the power to be determined during the pulse given the measurement of the average power of a modulated signal with a known duty cycle. DCC have improved stability, correction range, and operating frequency compared with mixed-signal and all-digital DCCs. In this analysis, the duty cycle correction circuits and their significance in Application Specific Integrated Circuit (ASIC) design, along with typical implementation methods, are discussed.

A 14 GHZ DELAY LOCKED LOOP WITH MINIMIZED PERIOD DELAY ERROR AND WORST 1.5% DUTY CYCLE ERROR

In many applications, the Delay Locked Loop (DLL) is used to improve the timing margin for better performance of the synchronous system. A precise 50′ duty ratio of the clock signal is essential to the DDR SDRAM, which needs both the rising edge and the falling edge of the clock to sample the data. The duty mismatch of the output clock in the DLL may be caused by the duty error of the external input clock or by the common mode voltage offset in the voltage-controlled delay line (VCDL). Many studies have presented the duty cycle corrector (DCC) to reduce the duty mismatch of the clock. This paper proposes a high-frequency DLL that generates multiplate clocks with a wide frequency range. The object of this research is to have +-1.5% duty cycle error at the output clock and, in locked state, less than 2% of clock period delay between 0- and 360-degree phases (delay error). This generator produces 8 phases at 14 GHz.

A High-Frequency and Low-Jitter DLL With Quadrature Error and Duty-Cycle Corrections Based on Asynchronous Sampling

This paper presents a quadrature error and duty-cycle correction circuit based on an asynchronous sampling technique. Sampling the multi-phased clocks provides their phase and duty-cycle information, which are then utilized to compensate for the quadrature and duty-cycle errors. The intrinsic down-conversion operation of the proposed sampling approach enhances the correction accuracy by mitigating circuit mismatch effects. The quadrature-error corrector (QEC) and duty-cycle corrector (DCC) circuits receive control signals generated from the asynchronous phase detectors and correct the clock outputs accordingly. Combined with a delay-locked loop (DLL), the proposed design is fabricated in a 40-nm CMOS process, consumes 7.2 mW, and occupies 0.023 mm. It achieves 0.837-ps RMS jitter and 1.68∘ maximum phase error from multiple chip samples.

A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line

Duty-cycle distortion may occur due to variations in the process, voltage, and temperature, or if the clock signal passes through clock buffers. To compensate duty-cycle distortion, a digital duty-cycle corrector (DCC) with counter-based half-cycle delay line (HCDL) is introduced. The HCDL of conventional edge combiner-type DCC requires a large area and makes the DCC unsuitable for applications that operate at a wide-range frequency, such as memory or ADC interfaces. The proposed counter-based HCDL reduces the silicon cost by repeating the delay line while maintaining the performance of the conventional DCC. The proposed DCC is divided into two operations. The training operation is performed for wide-range operation, followed by normal operation performed through the result of the training operation. A prototype chip fabricated in a 65nm CMOS process has an area of 0.0064mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 2.1mW at 1.6GHz. The measurement results show that the duty-cycle error is less than 0.89% over an input duty-cycle range of 20-80% for 50-1600MHz.

A 13 Gbps 1:16 deserializer ASIC for NICA multi purpose detector project

This paper presents the design and test results of a 13 Gbps 1:16 deserializer ASIC fabricated in a 55 nm CMOS technology for Nuclotron-based Ion Collider fAcility (NICA) Multi Purpose Detector (MPD) project. The deserializer would be used in the downlink data transmission of MPD readout system to recover the serial data from the back-end to the parallel data for the front-end. The ASIC adopts a tree-type structure, consisting of a high-speed data receiver (RXDATA), a high-speed clock receiver (RXCLK), four levels of demultiplexer (DEMUX) modules, clock dividers and 16 Low-Voltage Differential Signaling (LVDS) drivers. The demultiplexer modules are composed of different numbers of high-speed DEMUX unit and low-speed DEMUX unit. The high-speed DEMUX unit and the high-frequency clock divider adopt an optimized compressed current mode logic (CML) differential structure to ensure the bandwidth with limited voltage headroom. The low-speed DEMUX unit and the low-frequency clock divider use CMOS latch to save power consumption. The duty cycle correction (DCC) circuit and the clock aligner are employed in the clock paths to ensure the correct duty cycle and aligned clock edges. In the chip test, the ASIC receives 13 Gbps serial data and outputs 16 channels of 812.5 Mbps data correctly with wide-open eye diagram. The tested power consumption is 203 mA with 1.2 V power supply including the RXDATA, the RXCLK and the 16 channels of LVDS drivers, and the core power consumption is 122.7 mA.

Implementation of Modified Incremental Conductance MPPT A lgorithm in Grid Connected PV System Under Dynamic Climatic Conditions

Background: The main goal of the grid-connected Photo Voltaic (PV) system is to extract maximum power from the array with reduced loss by using an appropriate MPPT method. Methods: A boost converter topology with linear INCMPPT algorithm is used to provide maximum power of 100 kW from the solar PV array to the grid. The integral regulator in the modified algorithm minimizes the error and guarantees exact control of the duty cycle of the DC-DC converter to produce constant DC voltage 500V with a minimum error of 2V. This proposed methodology perfectly matches with the optimal design of the DC-AC converter (inverter) for grid integration. A three-level IGBT-based voltage source inverter and filters are designed to supply pure AC voltage to the existing 100 kW grid. Detailed simulation work is completed using MATLAB/ Simulink software to prove the effectiveness of the proposed algorithm under various temperature (25-50◦C) and irradiance (200-1000W/m2) levels. Findings: The proposed MPPT algorithm is simple and effective in reducing the error required for the duty cycle correction from 0.45 to 0.518 and eliminating the oscillations at MPP. By using this methodology, the output voltage of the boost converter is adjusted to match the reference value. The simulation results reveal the better performance of the grid-connected PV system with the modified incremental conductance MPPT method. This modified INC MPPT algorithm exactly controls the duty cycle of the boost converter to provide better settling time and low ripples in the grid parameters. Novelty: This article provides a simple and effective improved incremental conductance (INC) MPPT algorithm to minimize the tracking error (1.5%). No additional tuning and selection of parameters, computational burden and memory are required for the implementation of the proposed control algorithm. Keywords: Gridconnected photovoltaic (PV) system; Maximum power point tracking (MPPT); Voltage Source Inverter (VSI); Boost converter; Incremental conductance (INC)