Programmable delay line with inherent duty cycle correction

Abstract

In the recent HBM2E IO design, clock is transmitted differentially to the external DRAM and duty cycle distortion (DCD) could add to the differential clock due to traversing multiple stages in DRAM. At higher data rates, the DCD from the differential clock imposes restrictions on the timing margins. In current work, Tx clock path is added with DCC feature to compensate for any DCD errors introduced by the clock network in the external DRAM. Linearity of the DCC is critical metric when the clock is differential and running at high speed. A new programmable delay line with inherent DCC design with good linearity is presented in this paper.