Abstract
Impact of Read Enable (RE) signal's Duty Cycle Distortion (DCD) must be integrated in NAND to Flash Management Controller (FMC) SI simulation to predict system level performance accurately in multi-die, high performance systems. Assuming 50% duty cycle signal at the input to NAND driver is too optimistic. Both FMC and NAND contribute a portion of duty cycle distortion in the NAND read cycle. This paper identifies the gap in conventional SI simulation and describes how to reduce this gap in the simulation flow by including realistic RE DCD. Die level signals were measured for correlation purpose, and good correlation was observed between the measurements and simulations, demonstrating the importance of proposed changes.
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