Dummy Transistors Research Articles

A 19.5 GHz 5-Bit Digitally Programmable Phase Shifter for Active Antenna Arrays

This paper presents the design of a new phase shifter to be used in a receiver of active antenna array operating in the range from 17 GHz to 22 GHz. Beamforming is achieved by controlling the phase of the signal in each radiant element. In this context, the phase shift is obtained by the combination of a quadrature signal generator (QSG) and a variable gain amplifier (VGA). This work is focused on the design of a VGA which has a set of dummy transistors to keep the input and output impedance constant. The phase shifter is digitally programmable using a 5-bit word. The system was laid out using a 65 nm CMOS process, and the physical post-layout results show that the phase shifter achieves root mean square errors of 4.5° for the phase and 0.79 dB for the gain at a frequency of 19.5 GHz. A comparative analysis with other recently published phase shifters shows that the proposed phase shifter presents a good compromise between power consumption and accuracy.

A Highly Reliable, Dynamic Logic-Based Hybrid MTJ/CMOS Magnetic Full Adder for High-Performance and Low-Power Application

At deep sub-micrometer technology, CMOS circuits suffer from high leakage and have reliability issues due to process variation. Hybrid magnetic tunnel junction (MTJ)/CMOS circuits have been proposed to overcome these challenges. MTJs have zero standby power and are compatible with CMOS technology. In this article, a dynamic logic-based hybrid MTJ/CMOS magnetic full adder (MFA) has been proposed, which eliminates the error voltage appearing on output due to charge injection and clock feedthrough phenomenon, thereby enhancing the performance of MFA and making it more reliable. This effect is induced by the pMOS transistor, which is used as a switch to precharge the output nodes. The proposed MFA uses two dummy transistors, whose drain and source terminals are shorted to make them act as MOS capacitors, to absorb the error voltage introduced by the switch pMOS transistor due to charge injection and clock feedthrough, when turned OFF. Eliminating the error induced due to charge injection and clock feedthrough makes the amplification process faster and reduces the dynamic power consumption. Results are verified by performing transient and Monte Carlo simulations using cadence virtuoso with UMC 40 nm CMOS technology kit and compact model of perpendicular magnetic anisotropy (PMA) MTJ, which validates that the proposed MFA is highly reliable as it provides the error-free output and imparts better power–delay product (PDP) compared to previously proposed MFA.

10-Bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with a Phase-Locked Loop and Modified Bootstrapped Switch for a BLDC Motor Drive

In this paper, we present a successive approximation register (SAR) analog-to-digital converter (ADC) with a charge-pump (CP) phase-locked loop (PLL) and a bootstrapped switch, also called PLL-SAR ADC. To meet system-on-chip (SOC) and industrial requirements, the proposed SAR ADC and the control circuits of electric vehicles must be integrated into a single chip and be fabricated using the TSMC 0.25-μm 1P3M complementary metal oxide semiconductor (CMOS) high-voltage process. It is difficult to implement a high-speed SAR ADC with the TSMC 0.25-μm CMOS high-voltage process because it includes an N-type buried layer, which shorts all p-type metal oxide semiconductor field-effect transistor (PMOSFET) bodies together to withstand high voltages. In the proposed PLL-SAR ADC, two clock signals, an external clock signal and an internal clock signal from the CP-PLL, are provided to guarantee that a correct clock signal is fed. This design improves the robustness of the designed system. A monotonic capacitor-switching procedure is considered to reduce power consumption. Furthermore, a bootstrapped switch was added along with a dummy switch and a dummy transistor to eliminate disturbances in the input voltages and to improve the device’s anti-noise capability. Moreover, a two-stage dynamic comparator was used to prevent kickback noise induced by the parasitic capacitors. The measurements indicate that the signal-to-noise-and-distortion ratio, effective number of bits, power consumption, and chip area are 53.82 dB, 8.65 bits, 1.256 mW, and 1.261 × 0.975 mm2, respectively. The FoM is approximately 0.625 pJ/conv-step at 1.256 mW, 8.65 bits, and 5 MS/s. The high sampling rate of 5 MS/s and high accuracy of 8.65 bits are the main advantages of the proposed PLL-SAR ADC.

Threshold tuning DACs for pixel readout chips at the High Luminosity LHC

This work is concerned with the design and the characterization of digital-to-analog current converters, developed in a 65 nm CMOS technology, conceived for threshold tuning of front-end channels at the High-Luminosity LHC experiment upgrades. Two DAC designs were integrated in a small prototype chip, that was submitted in August 2018 in the framework of the RD53 developments. One of the DAC designs features a binary weighted architecture implemented with cascoded current mirrors and no dummy transistors, whereas the second one, sharing the same architecture, exploits regular current mirrors with dummy transistors. The prototype has been tested before and after exposure to X-rays up to a TID of 460 Mrad(SiO2). The main performance parameters of the two structures, namely DAC dynamic range, INL and DNL, are compared and discussed in the paper.

Pulse Quenching and Charge-Sharing Effects on Heavy-Ion Microbeam Induced ASET in a Full-Custom CMOS OpAmp

In this paper, charge-sharing effects on analog single-event transients are experimentally observed in a fully custom designed, 180-nm complementary metal-oxide-semiconductor (CMOS) operational amplifier by means of a heavy-ion microbeam. Sensitive nodes of the differential stage showed bipolar output transients that cannot be explained by single-node collection for the closed-loop characteristics of the circuit under test. The layout of these transistors is consistent with charge-sharing effects due to deposited charge diffusion. Implementation of linear modeling and simulations of multiple node collection between paired transistors of the input stage showed great coincidence with the obtained experimental waveforms, shaped as bipolar, quenched pulses. These effects are also observed due to dummy transistors placed in the layout. A simple parametrization at the simulation level is proposed to reproduce the observed experimental waveforms. Results indicate that charge-sharing effects should be taken into account during simulation-based sensitivity evaluation of analog circuits, as pulse quenching can alter the obtained results, and linear modeling is a simple approach to emulate simultaneous charge collection in multiple nodes by applying superposition principles, with aims of hardening a design.

Low noise and low power switched biased CSA with clocked reset and minimal PVT variation for APD based positron emission tomography

Switched biased technique is applied to implement a low noise and low power charge-sensitive amplifier (CSA) for avalanche photo-diode (APD) based positron emission tomography front-end application specific integrated circuit, designed in UMC 180 nm CMOS process. This technique pushes MOSFET to the verge of accumulation region during operating time, to reduce 1/f noise and power consumption. APD dark current compensation circuit is implemented with slow Trans-conductance (G-m) feedback loop to compensate up to 200 nA of dark current. Input and output reset functionality is implemented using NMOS switches coupled with dummy transistors. The CSA uses a core amplifier having dc gain of 60 dB, 144 kHz of minimum -3db bandwidth and 345 µW of maximum power consumption with 3.3 V supply voltage. The CSA converts 5---50pC of input charge to 0---2.6 V output while achieving 354pV of input RMS noise and 34e--- equivalent noise charge. Replica biasing technique is used to achieve minimal process, voltage, temperature variation in CSA. The complete design of CSA uses 105 µm × 220 µm of layout area.

Impact of glycerol on Zinc Oxide based thin film transistors with Indium Molybdenum Oxide electrodes

ABSTRACTThin-film transistors (TFT) were fabricated at a room-temperature (RT) with zinc oxide (ZnO) channel and indium molybdenum oxide (IMO) electrodes. To isolate the gate oxide and gate electrode influence on the device performance, common gate configuration on a commercial substrate with thermal SiO2 (100 nm) was selected. A threshold voltage (VTh) of 10 V and ION/IOFF ratio of 1 × 10-5 were obtained. Once the reference data was taken transistors were exposed to glycerol. Temporary changes in device characteristics were observed due to the influence of glycerol, a low conductivity medium. To exclude the possibility of sugar alcohol being the main conductor, measurement on dummy transistor electrode was performed retaining the distance between probes. The TFT device under test revealed ten times higher drain current but also a change in threshold voltage and leakage current. Transistors under glycerol influence were always open with the positive gate bias.

Novel Layout Technique for Single-Event Transient Mitigation Using Dummy Transistor

In this paper, a novel layout technique for single-event transient (SET) mitigation based on dummy transistors is proposed. Numerical simulations using technology computer-aided design with 90-nm twin-well CMOS technology show that the proposed layout technique can efficiently reduce SET pulsewidths. This layout design methodology is thoroughly discussed for the case of the inverter cell, and the discussion is then extended to other logic cells. We also compare the proposed layout technique with the “guard ring” (for P-hit mitigation) and the “guard drain” (for N-hit mitigation) layout techniques, and we find that not only does the proposed layout technique provide the benefit of greater SET mitigation but it also presents a smaller area penalty.

Design and characterization of a CMOS preamplifier for quantum well infrared photodetectors

A preamplifier based on the source-follower direct injection (SFDI) topology for use in read-out integrated circuits (ROIC) of quantum-well infrared photodetectors focal plane arrays (QWIP-FPA) is demonstrated. The fabricated circuit shows high linearity, high integration time (from hundreds of μs to few ms) and low current detection capabilities for a wide range of input current (order of few pA). This performance was achieved through the use of a Poly1-Poly2 capacitor that, although presenting some penalties in area consumption, provides a higher linearity, lower leakage current and higher temperature stability than all others capacitors found in literature. Secondary effects such as charge injection and clock feed-through are observed in the experimental results and classical techniques, like the use of DUMMY transistor, are shown to be effective in minimizing these effects and maximizing the linearity of the response. The overall results indicate that this circuit architecture has a great potential to be practically integrated in larger QWIP-FPA ROICs, showing an improved performance relating to previous works in literature.

Application of a low‐glitch current cell in 10‐bit CMOS current‐steering DAC

PurposeThe purpose of this paper is to describe the application of low‐glitch current cell in a digital to analog converter (DAC) to reduce the clock‐feedthrough effect and achieve a low power consumption.Design/methodology/approachA low‐glitch current switch cell is applied in a ten‐bit two‐stage DAC which is composed of a unary cell matrix for six most significant bits and a binary weighted array for four least significant bits (LSBs). The current cell is composed of four transistors to neutralize the clock‐feedthrough effect and it enables DAC to operate in good linearity and low power consumption. The prototype DAC is being implemented in a 0.35μm complementary metal‐oxide semiconductor process. The reduction in glitch energy and power consumption has been realized by preliminary experiment and simulation.FindingsCompared to conventional current cell, more than 15 per cent reduction of glitch energy has been obtained in this work. The DAC is estimated that differential nonlinearity is within 0.1 LSB and the maximum power consumption is 68 mW at the sampling frequency of 100 MHz.Originality/valueComparison with other conventional work indicates that the current cell proposed in this paper shows much better performance in terms of switching spike and glitch, which may come from the extra dummy transistor in cell and reduce the clock‐feedthrough effect.

A low-kickback-noise and low-voltage latched comparator for high-speed folding and interpolating ADC

A novel low-kickback-noise Class-AB latched comparator utilizing unilateralization technique is presented for high-speed folding and interpolating analog-to-digital converter (ADC).The load transistors are independent with the clock signal. So the comparator can suppress the kickback noise significantly and work at low power supply. Dummy transistors and neutralization technique are also introduced to further reduce the noise. The comparator is simulated in 0.18-µm standard digital CMOS technology. A very low kickback noise voltage of 0.14mV is realized at the differential input voltage of 300mV.The power dissipation is about 202µW at 1.8V supply voltage, 250MHz clock frequency.

Wide-range single-ended CMOS track-and-hold circuit

This paper investigates the performance of a MOS track-and-hold circuit as the front end of a wide input range and high-speed single-sided ADC. In order to reduce charge injection and clock feedthrough errors, a new technique for employing a dummy transistor in the bootstrapped switch of the track and hold circuit is introduced. Performance of the proposed circuit for the two cases of constant and non-linear hold capacitor is studied. It is also shown that how and when dummy switch and bulk switching method can improve the accuracy of the T/H.

Improved subthreshold slope method for precise extraction of gate capacitive coupling coefficients in stacked gate and source-side injection flash memory cells

Existing subthreshold slope methods are shown to be far from accurate in extracting gate capacitive coupling coefficient α G in stacked gate flash memory cells. The origin of the error is systematically identified: (i) process variations induced mismatch and (ii) underlying bulk capacitive coupling. To alleviate such drawbacks, a new version of the subthreshold slope method at room temperature is established: α G=0.06( n f− α B)/ s f, where the subthreshold swing s f is from flash memory cells, the subthreshold slope factor n f is from dummy transistors via threshold voltage against source-to-substrate bias measurement, and the bulk coupling coefficient α B is from a linear extension of the dimensional dependencies in the literature. The resulting α G of around 0.55 again agrees consistently with those dependencies and once drain and source coupling experiment is performed, the relation of ∑ α i ≈1 is achieved for all involved coupling coefficients α i 's. The sidewall source-side injection flash memory cells are also investigated. With the improved method, this manufacturing process is proved free of process variations issue and is characterized with α G of 0.374 and fringing capacitance of 0.204 fF.

A high-speed fully differential current switch

A high-speed differential-mode current switch is presented. The clock-feedthrough effect is reduced by swing-reduced drivers (SRD's) and neutralized by dummy transistors. With the use of SRD's, the switching transistors never operate in the triode region, which provides good matching of capacitance between the switching transistors and dummy transistors. The SRD's also reduce the possible large current spikes on the outputs of the current switch. Analysis shows this current switch is ideal for high-speed current-mode signal processing. A continuous-time switched-current /spl Sigma//spl Delta/ modulator using these current switches has been implemented in a 2 /spl mu/m CMOS process and achieved a 59 dB dynamic range with a 50 MHz clock.

A compact high-speed Miller-capacitance-based sample-and-hold circuit

The existing Miller-capacitance-based sample-and-hold circuit has been simplified into a compact one, achieved by replacing the operational amplifier in the Miller feedback circuit with a simple CMOS inverter. As a result, the area consumption is greatly reduced while maintaining the original advantages of high switching speed and high sampling precision. The on-chip test circuitry for the proposed compact sample-and-hold has been fabricated and characterized. Experimental results have shown that for a short clock transition time down to equipment limit of 1.8 ns, the sampling error becomes independent of the input over a small input voltage range of 1 V. This range can be substantially expanded by lowering the clock transition time, moreover, another compact Miller-capacitance-based sample-and-hold circuit with a dummy transistor included has been implemented on-chip and has experimentally exhibited a sampling error voltage of less than 6 mV over an input voltage range of 2.5 V. The spectrum behaviors of the compact circuits with and without a dummy transistor have been measured, showing an improvement on the quality of the circuit by increasing the clock frequency.

Characterization and improvement of GaAs HEMT analog switches for sampled-data applications

This paper presents design consideration and experimental comparison of GaAs HEMT analog switches for high-speed and high-precision sampled-data applications. At first, basic pass-transistor switches fabricated in a 0.5-/spl mu/m GaAs HEMT technology are measured for characterization of transient errors induced due to clock-feedthrough and charge transfer. In order to improve the switch dynamic performances, a dual dummy transistor compensation technique is used and related driver circuitry is developed. On-wafer measurements demonstrate that the improved switch provides a significant reduction of the transient errors, a reasonable dynamic range, and a high isolation. The switch with a 0.53 pF load capacitor achieves a total harmonic distortion below -55 dB and -38 dB at 10 MHz and 1.0 GHz clock frequency, respectively. >

Microwatt Switched Capacitor Circuit Design

The micropower CMOS implementation of the three basic components of switched capacitor circuits is discussed. Switches must be carefully designed to allow low voltage operation and compensation of clock feed-through by dummy transistors. Matched capacitors can be implemented in single polysilicon technologies primarily designed for digital micropower circuits. Excellent micropower amplifiers are realized by using simple one-stage circuits which take advantage of the special behaviour of MOS transistors in weak inversion. Noise is shown to be independent of current level which only influences the settling time. Various ways of improving the settling time while keeping a very low current drain are described. A method of calculating the noise of a biquadratic filter is followed by examples of a filter and of other switched capacitor circuits.