Improved subthreshold slope method for precise extraction of gate capacitive coupling coefficients in stacked gate and source-side injection flash memory cells

Abstract

Existing subthreshold slope methods are shown to be far from accurate in extracting gate capacitive coupling coefficient α G in stacked gate flash memory cells. The origin of the error is systematically identified: (i) process variations induced mismatch and (ii) underlying bulk capacitive coupling. To alleviate such drawbacks, a new version of the subthreshold slope method at room temperature is established: α G=0.06( n f− α B)/ s f, where the subthreshold swing s f is from flash memory cells, the subthreshold slope factor n f is from dummy transistors via threshold voltage against source-to-substrate bias measurement, and the bulk coupling coefficient α B is from a linear extension of the dimensional dependencies in the literature. The resulting α G of around 0.55 again agrees consistently with those dependencies and once drain and source coupling experiment is performed, the relation of ∑ α i ≈1 is achieved for all involved coupling coefficients α i 's. The sidewall source-side injection flash memory cells are also investigated. With the improved method, this manufacturing process is proved free of process variations issue and is characterized with α G of 0.374 and fringing capacitance of 0.204 fF.