A compact high-speed Miller-capacitance-based sample-and-hold circuit

Abstract

The existing Miller-capacitance-based sample-and-hold circuit has been simplified into a compact one, achieved by replacing the operational amplifier in the Miller feedback circuit with a simple CMOS inverter. As a result, the area consumption is greatly reduced while maintaining the original advantages of high switching speed and high sampling precision. The on-chip test circuitry for the proposed compact sample-and-hold has been fabricated and characterized. Experimental results have shown that for a short clock transition time down to equipment limit of 1.8 ns, the sampling error becomes independent of the input over a small input voltage range of 1 V. This range can be substantially expanded by lowering the clock transition time, moreover, another compact Miller-capacitance-based sample-and-hold circuit with a dummy transistor included has been implemented on-chip and has experimentally exhibited a sampling error voltage of less than 6 mV over an input voltage range of 2.5 V. The spectrum behaviors of the compact circuits with and without a dummy transistor have been measured, showing an improvement on the quality of the circuit by increasing the clock frequency.