Dummy Fill Research Articles

A Fine-Grained, End-to-End Feature-Scale CMP Modeling Paradigm Based on Fully Convolutional Neural Networks

Chemical mechanical polishing (CMP) planarizes the chip surface through a synergistic effect of chemical etching and abrasive polishing, and has become increasingly essential in modern semiconductor manufacturing. For better production yield, the industry seeks an accurate CMP model to identify, localize and control surface unevenness caused by the layout dependent effect (LDE) prior to fabrication, which provides valuable information for manufacturing-friendly designs, such as accurate hotspot prediction, design-rule optimization, and smart dummy fill. However, existing models are often overly coarse-grained and inaccurate: They are unable to utilize or analyze detailed topology information in a layout design, and can only characterize the post-CMP chip surface into a rough step-height model. The prediction resolution is also constrained by the featuring window size. In this paper, we propose a novel fine-grained and end-to-end feature-scale CMP modeling paradigm based on fully convolutional neural networks. The model directly analyzes the detailed layout topology without an explicit step of featuring parameter extraction, accurately predicts the rich chip surface micro-topography at a feature-scale precision. We designed and taped-out test chips under 28nm and 40nm processes. Experiments on silicon data demonstrated our model’s accuracy improvements of 65% to 76%, as well as its cross-process-node adaptability.

Automation of optimal metal density filling for deep sub micron technology designs

The locally adopted technique of Chemical-mechanical polishing (CMP) along with various other steps taken in design for manufacturing procedures employed for the fabrication of nano ICs, results in adverse impact on interconnecting wire parameters as well as device features. In order to enhance the manufacturability yield, performance predictability and also for getting the uniform chip layout a propos to prescribed density criteria; dummy fill insertion into layout is a mandatory step of contemporary manufacturing process. Full chip dummy fill is an iterative process which is time consuming and exponentially increases size of GDS. This paper discusses an algorithm which suggests a more sophisticated dummy-fill technique such that it optimizes the total number of metal fill by keeping a tradeoff between the fill requirement and need of design. The proposed algorithm will iterate automatically till a target density is reached with marginal increase to the size of the GDS. MENTOR GRAPHICS SVRF Calibre commands are used to develop the algorithm. PERL scripting is used to run the job automatically. The simulated experimental results points out that the proposed method renders a more balanced metal density distribution while using lesser dummy metal features. Besides this it shows an acceptable timing overhead.

A study on flare minimisation in EUV lithography by post‐layout re‐allocation of wire segments

The feature size in Integrated Circuits (ICs) has been scaling down aggressively, thereby posing more challenges in their manufacturability. Conventional immersion lithography using a laser of 193 nm wavelength produces layouts having distortions that degrade performance significantly. To overcome this bottleneck, Next-Generation Lithography (NGL) technologies are being developed. Extreme Ultraviolet Lithography (EUVL), one of the popular NGLs, which uses a light of 13.5 nm wavelength. However, irregularities on the photo reflective surface of clear-field masks used in EUVL, scatter the incident light and cause flare that in turn results in layout pattern distortions and critical dimension (CD) violations. One of the approaches to counter the effect of flare is to utilise dummy metal fills. But this incurs additional mask cost. Herein, a method to reduce the flare variation as well as the average flare distribution for a layout by perturbation of wire segments, without affecting performance at the post-layout phase, is proposed. The results show reductions of 20% and 11% on an average in the flare variation and flare mean, respectively, compared to that for the original layout for two different flare models studied on three standard sets of benchmark suites. Consequently, a reduction in the dummy fill demand of a similar magnitude is thus obtained.

Конструирование шин питания и заземления в интегральной схеме с вставкой фиктивного металлического заполнителя с учетом временных параметров

As dummy metal fill insertion is mandatory step for integrated circuits’ (IC) current manufacturing processes, many works are targeting better fill insertion with small coupling capacitance. However, with scaling technology trends, smaller IR drop is becoming more and more required, as its high value can lead to integrated circuit working failures. To ensure IR drop reduction, a new approach was proposed: while doing dummy fill insertion, firstly, metal shapes which are tied to power and ground nets were inserted and then timing aware dummy metal shapes were added. It has been established that power and ground metal fill shapes were creating shield layers, hence optimizing IR drop. Later it was found that timing aware dummy metal fill insertion was creating dummy metals for ensuring final metal ratio. Experiments have shown that with the use of proposed method, for 5 different designs IR drop has been reduced on average by about 11,9 %; however, placement and routing tool runtime has been increased by about 27,8 % and overall capacitance has been increased by about 4,4 %.

A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method

Dummy filling is widely applied to significantly improve the planarity of topographic patterns for the chemical mechanical polishing process in VLSI manufactures. The main challenge of dummy filling is balancing multiple objectives, such as fill amounts, planarity, parasitic capacitance, etc. An obvious drawback of traditional rule-based dummy filling methods is pattern densities, instead of post-chemical mechanical polishing (CMP) topographies, being included in optimization objectives. Although the quality of post-CMP topography strongly depends on pattern features of layouts, especially the density uniformity, however, experimental results show that chip surface variations are not exactly the same as density variations. In this article, a unified dummy fill insertion optimization framework is proposed, integrated with the multiple starting points-sequential quadratic programming (MSP-SQP) optimization solver, where all objectives are considered without approximation. Inside this framework, a full-chip CMP simulator is first integrated to evaluate the planarity of the chip surface. By selecting the initial points smartly with heuristic prior knowledge, the proposed method can be effectively accelerated. The effectiveness of the proposed algorithm is verified with the average 25.8% improvement of quality compared with rule-based methods.

Floating Random Walk-Based Capacitance Simulation Considering General Floating Metals

Accurate capacitance calculation for structures including floating metals is of great interest to both the modeling of interconnect wires and the verification of on-chip capacitors in the design of integrated circuit. The former problem involves regular-shape or cuboid floating dummy fills, and has been addressed with an existing fast algorithm based on floating random walk (FRW) method. The latter problem involves floating metals in more general and complex shape, and is crucial for the design of high-density metal–insulator–metal (MIM) capacitor which endures higher voltage. How to efficiently handle these general-shape floating metals becomes a challenge. In this paper, we first investigate the mechanism of the existing FRW-based approach for handling floating dummies, and then propose an approach based on the central difference formula for handling the general-shape floating metals. The proposed approach has comparable cost to the existing work, but is much more reliable and accurate. Experiments on the structures with floating dummies and MIM capacitor structures have validated the effectiveness and advantage of the proposed approach.

High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints

In deep-submicron very large scale integration manufacturing, dummy fills are widely applied to reduce topographic variations and improve layout pattern uniformity. However, the introduction of dummy fills may impact the wire electrical properties, such as coupling capacitance. Traditional tile-based method for fill insertion usually results in very large number of fills, which increases the cost of layout storage. In advanced technology nodes, solving the tile-based dummy fill design is more and more expensive. In this paper, we propose a high performance dummy fill insertion framework based on geometric properties to optimize multiple objectives simultaneously, including coupling capacitance, density variations and gradient. The experimental results for ICCAD 2014 contest benchmarks demonstrate the effectiveness of our methods.

MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts

Self-aligned multiple patterning, due to its low overlay error, has emerged as the leading option for 1-D gridded back-end-of-line (BEOL) in sub-14-nm nodes. To form actual routing patterns from a uniform “sea of wires,” cut masks are needed for line-end cutting or realization of space between routing segments. The line-end cutting results in nonfunctional (i.e., dummy fill) patterns that change wire capacitance, and hence design timing and power. Therefore, to remove such dummy fill patterns, extra 2-D block masks are used. However, 2-D block masks cannot remove arbitrary dummy fill patterns, due to design rule constraints on the block mask shapes. In this paper, we address the timing-aware optimization of 2-D block mask layouts under various sets of mask rules that are derived from mask patterning technology options (e.g., 193i and 193d) for foundry 7-/5-nm (N7/N5) BEOL. Our central contribution is a mixed integer linear programming (MILP) optimization that minimizes timing impact due to dummy metal segments while satisfying block mask rules and metal density constraints. We also propose a distributed optimization flow to improve the scalability. With our optimizer, we recover up to 84% of the worst negative slack impact from dummy segments, with up to 64% dummy removal rate. We further extend our MILP to a co-optimization of cut and block masks. This paper gives new insights into fundamental limits of benefit from emerging cut and block mask technology options.

3-D IC Interconnect Parasitic Capacitance Extraction With a Reformulated PGD Algorithm

Proper generalized decomposition (PGD) is a recently developed model-order reduction method based on the use of variable-separated representations. In this paper, space variable-separated PGD is applied on the 3-D capacitance extraction of interconnects in integrated circuits to reduce its computational complexity. To make the PGD solver feasible, the complex boundary conditions are simplified by a characteristic function technique. 3-D singular-value decomposition of the coefficient functions is avoided by using a reformulated PGD algorithm, and therefore, the proposed method can effectively deal with problems with inhomogeneous dielectric layers and dummy fills. Numerical examples are given to verify the method.

Analysis of Effective Material Properties of Metal Dummy Fills in a CMOS Chip

Analysis of Effective Material Properties of Metal Dummy Fills in a CMOS Chip

An Effective Chemical Mechanical Polishing Fill Insertion Approach

To reduce chip-scale topography variation, dummy fill is commonly used to improve the layout density uniformity. Previous works either sought the most uniform density distribution or sought to minimize the inserted dummy fills while satisfying certain density uniformity constraint. However, due to more stringent manufacturing challenges, more criteria, like line deviation and outlier, emerge at newer technology nodes. This article presents a joint optimization scheme to consider variation, total fill, line deviation, outlier, overlap, and running time simultaneously. More specifically, first we decompose the rectilinear polygons and partition fillable regions into rectangles for easier processing. After decomposition, we insert dummy fills into the fillable rectangular regions optimizing the fill metrics simultaneously. We propose three approaches, Fast Median approach, LP approach, and Iterative approach, which are much faster with better quality, compared with the results of the top three contestants in the ICCAD Contest 2014.

Toward defect-free fabrication of extreme ultraviolet photomasks

Defect-free fabrication of extreme ultraviolet (EUV) masks relies on the appropriate detection of native defects and subsequent strategies for their elimination. Commercial unavailability of actinic mask-blank inspection systems motivates the identification of an optical inspection methodology most suitable for finding relevant EUV blank defects. Studies showed that 193-nm wavelength inspection found the greatest number of printable defects as compared with rival higher-wavelength systems, establishing deep ultraviolet inspections as the blank defectivity baseline for subsequent mitigation strategies. Next, defect avoidance via pattern shifting was explored using representative 7-nm node metal/contact layer designs and 193-nm mask-blank inspection results. It was found that a significant percentage of native defects could be avoided only when the design was limited to active patterns (i.e., layouts without dummy fill). Total pattern-defect overlap remained ≤5 when metal layer blanks were chosen from the top 35% least defective substrates, while the majority of blanks remained suitable for contacts layers due to a lower active pattern density. Finally, nanomachining was used to address remaining native/multilayer defects. Native catastrophic defects were shown to recover 40% to 70% of target critical dimension after nanomachining, demonstrating the enormous potential for compensating multilayer defects.

A 460‐GHz CMOS substrate‐integrated‐waveguide slot‐antenna design

ABSTRACTA design of a 460 GHz substrate‐integrated‐waveguide (SIW) slot antenna in a 65‐nm CMOS process is presented in thisarticle. The size of the antenna is 380 μm × 224 μm. An inductor identification layer is placed in the layout to reduce the internal metal density requirements significantly. The proposed antenna, which includes metal dummy fill to be compliant with the 65 nm process design rules, was simulated using HFSS. The antenna simulated with a 0.5 mm Si substrate has a maximum gain of 0.09 dBi and a radiation efficiency of 29.1%. The bandwidth of S11 below −10 dB is 25.3 GHz. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:347–351, 2016

Watermarking in Hard Intellectual Property for Pre-Fab and Post-Fab Verification

A manufacture-ready layout is vulnerable to misappropriation when it is either fabricated as a chip in a fabrication facility, or reused in a system-on-chip house. We propose an intellectual property protection (IPP) scheme IPP_MRL for protection of m anufacture- r eady l ayout against unauthorized reuse and inclusion of Trojans. The IPP_MRL inserts watermarks in the layout according to designer’s signature with an effect of tuning the delays at selected scan flip-flops. Certain dummy fills are reoriented in the neighborhood of selected net segments and it causes fine tuning of delay; certain other selected net segments are resized for coarse change in delay. The IPP_MRL not only verifies the watermark in the layout, but also captures its effect as delay fault-induced responses from the packaged chips, fabricated from the watermarked layout, by applying a faster test clock. Due to the controlled effect of watermarking on delay, responses are resilient against process and temperature variation, but capable of detecting hardware Trojan. The method is adaptive to device aging. The results for ISCAS’85 and ISCAS’89 benchmark circuits show that the overhead of watermarking on circuit delay is less than 0.05% and the probability of true false or false true can be at most $\sim 10^{-6}$ .

Smart Review Sampling Methodology in Huge Inspection Results

The defect inspection results for advanced technology nodes have extremely high defect counts frequently. Therefore, the defect review Pareto get high false rate due to the SEM non-visual defects, nuisance defects, or dummy fill patterns by traditional review sampling methodology. An integrated smart review sampling methodology is proposed to resolve the high false rate issue and dig out the DOIs and POIs effectively in huge big inspection results with aid of design data base.

AN IMPROVED RULE-BASED DUMMY METAL FILL METHOD FOR 65 NM ASIC DESIGN

Chemical-mechanical polishing (CMP) is an essential process in deep-submicrometer LSI manufacturing to achieve Chip's planarization. It includes two processes: back-end-of-line (BEOL) and front-end-of-line (FEOL). This paper focuses on the problem of BEOL in 65 nm copper process. Although model-based dummy metal fill has become a tendency recently, the proposed improved rule-based dummy fill is appropriate still. A middle scale design is used for simulation. The metal density, oxide thickness, copper thickness, capacitance variation and variation of layout data size were investigated. The results show that improved rule-based dummy fill and model-based dummy fill have the same planarization, and proposed method has small capacitance variation. The GDS file size of the proposed rule-based fill is less than the model-based fill's.

A Novel Design Flow for Dummy Fill Using Boolean Mask Operations

Dummy fill has been demonstrated to be an effective technique to reduce process variation and improve manufacturability for advanced integrated circuit (IC) designs. However, the computation load, often several days for a realistic IC design, is a significant portion of the cycle time for delivering first silicon on new or modified designs. In this paper, we propose a novel design flow and dummy-fill algorithm based on Boolean operations, which greatly improves computational efficiency and pattern density uniformity, and enables dummy generation to be combined with the mask-preparation Boolean operations performed by the mask-fabrication facility. Mask data preparation can be performed in parallel with dummy generation and post-dummy simulation checks at the design house, resulting in improved first-silicon cycle time. Experimental results demonstrate these benefits in the context of an advanced foundry process technology.

Study of Optimal Dummy Fill Modes in Chemical–Mechanical Polishing Process

Chip surface topography after chemical-mechanical polishing (CMP) process is greatly influenced by the layout geometric characteristics, such as line width and line space. In order to improve surface topography, dummy fills are often inserted between interconnects. However, this will increase coupling capacitances between interconnects and deteriorates the timing and signal integrity of the chip. In this paper, one flow to acquire optimal dummy fill modes is proposed for both better planarity and less capacitance increment in specific process. As an example of using this flow, we designed test patterns with different fill modes and measured their surface topography and coupling capacitances after the CMP process. Experiment results are displayed and analyzed, and fill guidelines for both better planarity and less coupling capacitance are proposed based on the results. A possible optimal fill mode is also acquired based on the guidelines. In our flow, only one test run is needed in each process, and then all the products run in this process can use these optimal fill modes.

An efficient method for gradient-aware dummy fill synthesis

In advanced VLSI fabrication, dummy fill is widely employed to solve the pattern dependent manufacturability issues. In this paper, a new linear programming formulation for dummy fill synthesis is proposed, which takes more consideration to the density gradient besides the pattern density. Based on the covering linear programming (CLP), a fast iterative approximation scheme is designed to solve this newly formulated problem. The complexity of the new method is proved to be O(n2log(n)). Experimental results demonstrate the effectiveness of the new formulation, and show good accuracy and time efficiency of the proposed method. Compared with the ordinary LP method, speedup over magnitude is achieved with the acceptable overfill amount.

A Resilient Authentication and Trojan Detection Technique for Hard IP

A manufacture-ready design layout of a chip is vulnerable to authentication threats and infection with trojan horse in its fabrication facility or in a SoC house. The existing countermeasures are sensitive to process variation. We propose a layout watermarking scheme through reorientation of few dummy fills in the interconnect layer and resizing of few net segments. Layout watermarking is so performed that it has a controlled delay effect on the active paths leading to certain scan flip-flops chosen judicially. This delay effect can be captured as delay fault induced responses from the packaged chip while tested with a faster clock and a particular test vector pair, but the difference of post-marking delay with respect to the test clock period remains more than the effect of process variation. Results on overhead of watermarking and its robustness for ISCAS’85 benchmark circuits are encouraging.