A Fine-Grained, End-to-End Feature-Scale CMP Modeling Paradigm Based on Fully Convolutional Neural Networks

Abstract

Chemical mechanical polishing (CMP) planarizes the chip surface through a synergistic effect of chemical etching and abrasive polishing, and has become increasingly essential in modern semiconductor manufacturing. For better production yield, the industry seeks an accurate CMP model to identify, localize and control surface unevenness caused by the layout dependent effect (LDE) prior to fabrication, which provides valuable information for manufacturing-friendly designs, such as accurate hotspot prediction, design-rule optimization, and smart dummy fill. However, existing models are often overly coarse-grained and inaccurate: They are unable to utilize or analyze detailed topology information in a layout design, and can only characterize the post-CMP chip surface into a rough step-height model. The prediction resolution is also constrained by the featuring window size. In this paper, we propose a novel fine-grained and end-to-end feature-scale CMP modeling paradigm based on fully convolutional neural networks. The model directly analyzes the detailed layout topology without an explicit step of featuring parameter extraction, accurately predicts the rich chip surface micro-topography at a feature-scale precision. We designed and taped-out test chips under 28nm and 40nm processes. Experiments on silicon data demonstrated our model’s accuracy improvements of 65% to 76%, as well as its cross-process-node adaptability.