Dual Work Function Metal Gate Research Articles

Trap-Induced Data-Retention-Time Degradation of DRAM and Improvement Using Dual Work-Function Metal Gate

Data retention time distribution of the dynamic random-access memory cell transistor of the 20-nm technology generation has been investigated using the physics-based statistical simulation. Traps cause high leakage current of the leaky cells; however, we found that the reduction of trap is not effective in improving the refresh cycle. Therefore, an effective method is needed to overcome the retention time degradation due to the traps. This study shows that the data retention time of the tail cells can be increased more than 50% by adopting the dual work function metal gate structure.

A 2-D Analytical Modeling of Dual Work Function Metal Gate MOSFET Using High-K Gate Dielectric with Enhanced RF/Analog Performance for Low Power Applications

A 2-dimensional electrostatic potential modeling of fully depleted channel, with high-k based dual work function double gate (DWFDG) MOSFET, has been developed in this paper. The expression for electrostatic potential of DMDG has been developed using 2-D Poisson’s equation with appropriate device boundary conditions along the device gate length. The high-k based DWFDG MOSFET shows a significant decrease in short channel effects (SCEs), by using step in electrostatic potential near the interface of gate materials (M1) and (M2). The impact of device limitations such as electrostatic potential with oxide thickness, channel thickness, different gate bias and drain bias on the capability of the device has been examined using novel analytical model. The validation of the analytical modeling results are verified with numerical simulation by using 2-dimentional Sentaurus TCAD device simulator. In addition, the simulation has been performed for finding analog performances of the proposed device as compared with conventional device. The significant improvement in drain current, Ion/Ioff ratio, output conductance and gm/Ids have been observed. Hence, the simulation results shows that the proposed device is best suitable for faster switching and low power applications.

Metal Wet Etch Issues and Effects in Dual Metal Gate Stack Integration

This article discusses metal wet etch issues and their effects on high-/metal films in dual work function metal gate stack integration. A versatile process using metal wet etch has been demonstrated to integrate dual metal gate complementary metal oxide semiconductor (CMOS) devices (Z. B. Zhang et al. , in 2005 Symposia on VLSI Technology and Circuits, Kyoto , Japan, June 14–18 , 2000). Different high-/metal films, combinations of films, etch selectivity, thermal stability, interactions among the films, and finally, surface conditions have made the implementation of metal wet etch challenging. Here, representative results using , , in situ steam generated silicon oxide , , Ta, , , , amorphous silicon (a-Si), and tetraethylorthosilicate in dual metal CMOS processing are presented.

Continuous and Precise Work Function Adjustment for Integratable Dual Metal Gate CMOS Technology Using Hf–Mo Binary Alloys

We demonstrate for the first time a continuous and almost linear work function adjustment between 3.93 and 4.93eV using Hf/sub x/Mo/sub (1-x)/ binary alloys deposited by co-sputtering. In view of the process integration, dual work function metal gate technology using Mo and Hf/sub x/Mo/sub (1-x)/ formed by metal intermixing was proposed. Work function values were verified to be a function of the thickness ratio and accurate work function adjustment can be possible. Furthermore, one can be allowed to get around the thermal stability issue by choosing an appropriate total metal thickness corresponding to the thermal budget subsequent to gate deposition, since the thermal budget required for metal intermixing depends on the total metal thickness.

Nickel Silicide Work Function Tuning Study In Metal-Gate CMOS Applications

ABSTRACTMid-gap work function (∼4.7eV) for mono-nickel-silicide (NiSi) was obtained by extrapolating flat band voltages of metal-oxide-semiconductor (MOS) capacitors with different gate oxide thickness. Both silicidation temperature and time can affect the nickel silicide work function as a result of different Ni:Si ratio close to the gate oxide interface. Arsenic implantation into the polysilicon before silicidation can shift the NiSi work function towards the silicon conduction band, which makes it suitable for high performance NMOS applications. The physical mechanism responsible for this work function shift is arsenic pile-up at the oxide interface during the nickel silicidation process. Therefore, dual work function metal gate can be obtained by using a single gate full silicidation process. Silicidation temperature and time also affect the work function shift from arsenic dopant, and the incomplete gate silicidation can have the maximum work function modification effect. Arsenic activation temperature before silicidation was found to have a significant effect on the work function shift. Un-annealed samples exhibit a minimum shift in work function due to the low dopant pile-up concentration at the oxide interface.

Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion

In this letter, we present dual work function metal gate complementary metal-oxide semiconductor (CMOS) transistors with thin SiO/sub 2/ gate dielectric fabricated through the interdiffusion of nickel and titanium. The threshold voltage of the n-MOS devices is determined solely by Ti, while the threshold voltage of the p-MOS devices is determined by the Ni-rich alloy of Ti and Ni. The advantage of this new approach is that low threshold voltages for surface-channel n-MOS and p-MOS transistors can be achieved simultaneously. At the same time, the integrity of the gate dielectric is preserved since no metal has to be etched from the surface of the gate dielectric. With gate depletion eliminated, these transistors exhibit high inversion charge and drive current.