Dual Supply Voltage Research Articles

New, Fast, High-Performance Level Shifter for Buck DC-DC Converter in 180nm CMOS Technology

To reduce power dissipation, the dual supply voltage approach is required for analog circuits in the on-chip integrated circuits. In this paper, a novel circuit of the level shifter for Buck DC-DC Converter using cross-coupled configuration is presented. The proposed work of this paper uses this level shifter to converter voltage of 1.8V to 5V at 180 nm CMOS Technology in Cadence Virtuoso Tool. The propagation delay, energy/transition, and static power were 182.42pS, 0.01 fJ/Transition, and 6 fW, respectively. The final design area is only 60.142 μm2.

A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction

This article presents a 60-MS/s 5-MHz BW noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) with an integrated highly linear input buffer in a 40-nm CMOS process. A dynamic level-shifting (DLS) technique is proposed to adaptively adjust the output common-mode voltage of the integrated input buffer for different operation phases, achieving the optimal linearity while alleviating the voltage breakdown problem at the capacitive digital-to-analog converter (CDAC) top plate. The mismatch-error-shaping (MES) technique is utilized to minimize the CDAC mismatch, which also generates undesired inter-symbol-interference (ISI) errors as a side effect. An ISI-error correction (IEC) technique is proposed to mitigate this problem and further improve the linearity. Both foreground and background calibrations are adopted in the subranging ADC and the NS filter to improve the gain accuracy. This SAR ADC prototype, with an integrated input buffer driving a 4.4-pF CDAC within 2.7 ns, achieves signal-to-noise ratio (SNR)/signal-to-noise-and-distortion ratio (SNDR)/spurious-free dynamic range (SFDR)/dynamic range (DR)/total harmonic distortion (THD) of 85.4 dB/84.2 dB/97.3 dBc/86.4 dB/−92.9 dBc while consuming 8.06 mW from 2.5- and 1.1-V dual supply voltages. The Walden FoM (FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {W}}$ </tex-math></inline-formula> ) and figure-of-merit (FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {S}}$ </tex-math></inline-formula> ) are 60.6 fJ/conv.-step and 172.1 dB, respectively.

A High-Speed Low-Energy One-Trit Ternary Multiplier Circuit Design in CNTFET Technology

Contemporary system-on-chip-based applications are battery-powered. To increase the operation time, they need various low-power/energy circuits. Carbon nanotube field-effect transistor (CNTFET) is a potential alternative to complementary metal-oxide-semiconductor for power/energy-efficient circuits implementation due to offering high performance. Another way to reduce power/energy consumption in a circuit is to use multiple-valued logic, especially ternary logic, which has three logical states. This paper presents a novel 1-trit ternary multiplier circuit with 23 transistors based on only unary operators of the ternary logic system and the dual-supply voltages technique. The proposed design does not use the ternary decoder/encoder, logic gates, cascading transmission gates, and ternary multiplexer to reduce the transistors count, delay, power, and energy. The Stanford CNTFET model in the 32 nm technology node is used to simulate the proposed design. The delay, power, and delay-power-product (PDP) of the proposed design at 0.9 V are 0.026 ns, 0.139 μW, and 3.614 aJ, respectively. It offers improvements between 50% and 61.19% in delay and between 52.72% and 59.75% in PDP compared to previously published multiplier circuits, which are based on the dual-supply voltages and use 23 transistors. These improvements make the proposed design a good candidate for the design of the next generation of multiplier circuits in arithmetic blocks.

Categorization and evaluation of voltage sag control methods and equipment: A study

Voltage sags have emerged as major problems in power quality in the recent years and the categorization of methods and tools available for reducing voltage sag is becoming increasingly crucial. Modern approaches and tools for minimizing voltage sag are based on an extensive research, aimed at developing effective categorization techniques to assist end users in selecting the most suitable tools and settings. To begin, this research provides a comprehensive assessment of the existing voltage sag control methods and equipment. Furthermore, it presents a classification scheme that divides voltage sag control strategies into three groups: those implemented by the power provider, the customer, and the equipment manufacturer. A classification system for voltage sag control equipment based on the number and type of power supply, taking into account the variations between single and dual power supply voltage sag control devices is also proposed. Additionally, to assist consumers in selecting the optimal device, this research demonstrates how primary voltage sag control equipment utilizes the preventive measures and an integrated software.

Investigation on Transient Ionizing Radiation Effects in a 4-Mb SRAM With Dual Supply Voltages

The impact of transient ionizing radiation effects on a 4-Mb static random access memory (SRAM) circuit which has an input–output (IO) supply voltage and a core supply voltage was studied. The experimental results indicate that a longer time is required to restore minimal operating voltage for core supply voltage. Based on the 180-nm bulk CMOS technology, 3-D mode numerical simulations with technology computer-aided design (TCAD) show that the parasitic bipolar effect plays a significant role in discrepancy in the recovery process between supply voltages. This effect will be discussed in depth in this article, and the simulation results illustrate that the n-well contact has a great impact on the operation mode of parasitic bipolar. Meanwhile, the supply voltage disturbance mitigation methods are presented through improving power supply voltage and placing more n-well contacts.

Operational Amplifier Design Employing DTMOS Technique with Dual Supply Voltages

An operational amplifier (OPAMP) for portable devices with dual supply voltage is presented in this work. The design is realized with a 600[Formula: see text]mV supply for the core design and a 1.8[Formula: see text]V supply for the biasing circuit to improve input common mode range (ICMR), gain, and common mode rejection ratio (CMRR). The designed amplifier is implemented with dynamic threshold voltage MOSFET (DTMOS) transistors to decrease power consumption and increase the performance of the design. The power consumption of the core design is obtained as 2[Formula: see text][Formula: see text]W while the biasing circuitry consumes 7.38[Formula: see text][Formula: see text]W. The application of different supply voltages has greatly increased the gain of the circuit, where the circuit exhibits 100.2[Formula: see text]dB DC gain and 3.41[Formula: see text]MHz gain bandwidth product (GBW). CMRR of the designed circuit is 84.22[Formula: see text]dB. The simulations are performed in Cadence environment with 0.18[Formula: see text][Formula: see text]m CMOS technology.

$$\alpha$$-order universal filter realization based on single input multi-output differential voltage current conveyor

Two voltage-mode topologies single input multi-output universal fractional filters with high input impedance are proposed. The proposed analog filters consist of three DVCC+ blocks, two grounded capacitors and two resistors targeting the minimum passive elements. The proposed topologies provide a realization for all standard fractional filter functions (HP, LP, BP, AP and notch filter). The effect of Fractional order on filter responses in the range of $$\alpha$$ from 0.7 to 1.2 was studied. Fractional order has been investigated for different filter responses in terms of cutoff, gain, phase and noise. The central frequency was designed to be 110 KHz for the first topology, while that of the second topology is around 100 KHz. The proposed filters are simulated using Cadence TSMC 130nm with dual supply voltages $$\pm \,0.75V$$ . A performance comparison between the proposed topologies and the topologies in the literature shows that the proposed architecture gives an acceptable performance.

Silicon Photomultiplier Sensor Interface Based on a Discrete Second Generation Voltage Conveyor.

This work presents the design of a discrete second-generation voltage conveyor (VCII) and its capability to be used as electronic interface for silicon photomultipliers. The design addressed here exploits directly at the transistor level, with commercial components, the proposed interface; the obtained performance is valuable considering both the discrete elements and the application. The architecture adopted here realizes a transimpedance amplifier that is also able to drive very high input impedance, as usually requested by photons detection. Schematic and circuital design of the discrete second-generation voltage conveyor is presented and discussed. The complete circuit interface requires a bias current of 20 mA with a dual 5V supply voltage; it has a useful bandwidth of about 106 MHz, and considering also the reduced dimensions, it is a good candidate to be used in portable applications without the need of high-cost dedicated integrated circuits.

FIN-FET BASED HIGH GAIN OP-AMP WITH SLEW RATE ENHANCEMENT IN 45-NM REGIME

In this paper dynamic biasing technique is used for the enhancing the slew rate of the designed Op-Amp. The proposed FinFET based Op-Amp has been verified through Hspice simulator in the standard 45nm Silicon on Insulator FinFET library. The proposed op amp has two stages Miller compensated configuration. A biasing circuit (DSB circuit) is used for dynamic switching of the biasing voltage of the op amp. This leads to lower power consumption, wide ICMR range, and high gain stability. The proposed op amp has a power consumption of 661.83 μW. It has a dual supply voltage of -1.0V and 1.0V. The input common mode range (ICMR) is -800 mV to +900 mV. The Op-Amp has a slew rate of 1.5 KV/μs. Voltage gain of the op amp is 90.4dB. Due to the use of SOI FINFET devices the op amp has relatively less leakage current as compared to similar bulk MOSFET device op amps. The op amp has unity gain bandwidth of 1.27 GHz. Thus, it can be used to transmission and processing of audio and video signals.

A General Structure and High-Performance Dual-Edge Triggered Level Converting Flip–Flop Based on BiCMOS

Dual supply voltage scheme provides very effective solution to cut down power consumption in digital integrated circuits design, where level converting flip–flops (LCFF) are the key component circuits. In this paper, a new general structure and design method for dual-edge triggered LCFF based on BiCMOS is proposed, according to that PNP-PNP-DELCFF and NPN-NPN-DELCFF are designed. The experiments carried out by Hspice using TSMC 180 nm show proposed circuits have correct logic functions. Compared to counterparts, proposed PNP-PNP-DELCFF gains improvements of 6.7%, 96.0%, 86.0% and 28.5% in D-Q Delay, 50.0%, 16.0%, 12.6% and 10.8% in product of delay and power (PDP), respectively. NPN-NPN-DELCFF gains improvements of 5.1%, 93.0%, 83.2% and 26.5% in D-Q Delay, 39.7%, 7.9%, 5.0% and 3.4% in PDP, respectively. Furthermore, proposed circuits have better drive ability.

Performance analysis of a solar‐powered water pumping using improved SIDO buck–boost converter

This study proposes a low-cost solar-powered water pumping system (SPWPS) utilising a proposed single-input dual-output (SIDO) buck–boost converter with an efficient control technique for the switched reluctance motor (SRM) drive. The newly designed buck–boost converter provides a continuous input and output current to the motor with a low ripple content. This converter is also capable to minimise the size of DC-link capacitor and to provide a balanced dual output voltage supply. Owing to the fundamental frequency switching of a split DC mid-point converter, there is a considerable reduction in the semiconductor losses and provides an opportunity to eliminate the sensors from the motor side. In addition, an improved perturb and observe (P&O) maximum power point tracking (MPPT) technique is also implemented in proposed system. The implemented MPPT algorithm has drift-free operation and an ability to control the pumping rate also at maximum PV power generation, which is usually difficult in standalone water pumping system. Test results are presented on an 875-Wp PV array fed a 1 hp pump to demonstrate sound agreement between the simulated and test results of proposed system.

A Dual-Supply Two-Stage CMOS Op-amp for High-Speed Pipeline ADCs Application

In this brief, a dual-supply two-stage op-amp is proposed for a 12-b 1 GS/s pipeline ADC, which is composed of a low-voltage supply pre-amplifier and a high-voltage supply amplifier. Its closed-loop bandwidth reaches to 5.2 GHz, and the phase margin is larger than 60°. The closed-loop amplifier can settle to 99.95% accuracy within 230 ps, which satisfies the harsh requirements of the first-stage MDAC. The proposed op-amp was employed in a single-channel 12-b 1 GS/s pipeline ADC. The ADC is powered by 1.3 V and the op-amp is powered by dual-supply voltage of 1.3 V and 2.5 V. The ADC fabricated in 65 nm CMOS process consumes 360 mW at 1 GS/s. It achieves an SNDR of 61.9 dB and an SFDR of 72.6 dB with 30 MHz input signal, while maintaining an SNDR > 56.0 dB and SFDR > 69.0 dB in the entire 500 MHz Nyquist band.

A Watt-Level Quadrature Class-G Switched-Capacitor Power Amplifier With Linearization Techniques

A 30.1-dBm quadrature transmitter is implemented based on Class-G IQ-cell-shared switched-capacitor power amplifier (SCPA) and voltage mismatch compensation techniques for dual-supply voltage in a Class-G SCPA. For the Class-G operation in the IQ-cell-shared quadrature SCPA, a merged cell switching (MCS) technique comprising vector amplitude switching (VAS) and vector phase switching (VPS) is proposed. The VAS boosts system efficiency (SE) by enabling the Class-G operation with multiple supply voltages and the VPS conserves vector information in the merged cells that process the quadrature vectors. The linearization technique for Class-G SCPA minimizes the distortion that arises from the supply-voltage mismatches in a multiple supply-voltage system. Two SCPAs are coupled with a power combining transformer to achieve a watt-level output power. A time-domain interpolation minimizes the spectral image. The prototype SCPA, fabricated in a 65-nm CMOS, achieves peak output power and SE of 30.1 dBm and 37.0%, respectively. It achieves error vector magnitude (EVM) of −40.7 dB (−40.3 dB) and SE of 14.7% (18.3%) at an average output power of 19.5 dBm (22.5 dBm) with 802.11g 64-QAM OFDM signal with 10.6 dB peak-to-average power ratio (PAPR) (20-MHz single-carrier 256-QAM signal with 7.6-dB PAPR).

High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits

Recently, the demand for portable electronics and embedded systems has increased. These devices need low-power circuit designs because they depend on batteries as an energy resource. Moreover, multi-valued logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption. Therefore, this paper proposes new ternary circuits aiming to lower the power delay product (PDP) to save battery consumption. The proposed designs include new ternary gates [standard ternary inverter (STI) and ternary NAND (TNAND)] and combinational circuits [ternary decoder (TDecoder), ternary half-adder (THA), and ternary multiplier (TMUL)] using carbon nano-tube field-effect transistors (CNFETs). This paper employs the best trade-off between reducing the number of used transistors, utilizing energy-efficient transistor arrangement such as transmission gate, and applying the dual supply voltages (V dd and V dd /2). The five proposed designs are compared with the latest 15 ternary circuits using the HSPICE simulator for different supply voltages, different temperatures, and different frequencies; 180 simulations are performed to prove the efficiency of the proposed designs. The results show the advantage of the proposed designs in reduction over 43% in terms of transistors' count for the ternary decoder and over 88%, 99%, 98%, 86%, and 78% in energy consumption (PDP) for the STI, TNAND, TDecoder, THA, and TMUL, respectively.

A 20 k-to-100kS/s Sub-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;W 9.5b-ENOB Asynchronous SAR ADC for Energy-Harvesting Body Sensor Node SoCs in 0.18-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;m CMOS

This brief presents an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for energy-harvesting body sensor node system-on-chips applications. To improve the power efficiencies of analog and digital blocks independently, a dual-supply voltage scheme is adopted, and a clock-to-Q delay compensator is proposed to realize the timing-calibration-free asynchronous operation with scalable supply voltages. For a maximum sampling rate of 20 kS/s, the SNDR is increased by 3 dB and the power consumption of the SAR logic is decreased by 37%, improving the FoM $_{\text{W}}$ by 26% with the analog and digital supply voltages of 0.6 V and 0.35 V, compared with the single supply of 0.4 V. To obtain a high effective number of bits (ENOB), the ADC exploits a current-biased dynamic comparator and a capacitive DAC with a modified partial common-centroid layout. With a DNL of +0.18/−0.2 LSB and an INL of +0.26/−0.25 LSB, the ADC achieves an ENOB of 9.64 bits at a sampling rate of 100 kS/s, exhibiting power consumption of 562 nW. The prototype ADC is fabricated in 0.18- ${\mu }\text{m}$ CMOS technology, occupying an area of 0.0468 mm2.

Circuit power optimization using pipelining and dual-supply voltage assignment

Power is one of the most important metrics in the modern integrated circuit design. We optimize the circuit power using two major approaches, pipelining and dual-supply voltage (dual-Vdd) assignment. To improve power efficiency, we have designed a new pipelining to reduce the number of gates need to be assigned to the high supply voltage when combined with the dual-Vdd assignment. Our overall design is tested on a set of standard ISCAS-85 benchmark circuits using an industrial cell library. An average power saving of more than 10% under a specified target delay is observed.

Ultra-low-power bulk-driven fully differential subthreshold OTAs with partial positive feedback for Gm-C filters

This paper presents an ultra-low-power, bulk-driven, source-degenerated fully differential transconductor (FD-OTA), operating in subthreshold region. The source-degeneration (SD) and bulk-drive ensure linearity and rail-to-rail input swing. The flipped voltage follower and SD resistor perform V–I conversion in input core with power efficient class AB mode of operation. The reduction in open loop gain and gain bandwidth (GBW) of bulk-drive is compensated by applying partial positive feedback at diode connected MOSFET pair. The current gain from input core to output load side is set (1:1) in OTA1 and (1:4) in OTA2. The OTA2 offers increased transconductance and GBW whereas self-cascode load increases the output impedance and overall gain of the FD-OTAs. Both the input core and common source self-cascode load operate in class AB mode so these FD-OTAs provide enhanced slew rates. These OTAs have been employed to implement Biquadratic low-frequency Gm-C filter suitable for bio-signal applications. The proposed OTA2 has used dual supply voltage of ± 0.3 V and dissipates around 70 nW power and provides 62 dB FD-open loop gain with GBW of 7.73 kHz while driving the FD-load of 2 × 15 pF. The Cadence VIRTUOSO environment using UMC 0.18 µm CMOS process technology has been used to simulate the proposed circuit. The Simulation results verified fully differential total harmonic distortion of − 72 dB, for 1.2 Vp–p signal at 200 Hz frequency in unity gain configuration with resistive degeneration of 1 MΩ for OTA1.

Investigation and Analysis of the Simultaneous Switching Noise in Power Distribution Network with Multi-Power Supplies of High Speed CMOS Circuits

The paper studies a simultaneous switching noise (SSN) in a power distribution network (PDN) with dual supply voltages and two cores. This is achieved by reducing the admittance matrix Y of the PDN then calculating frequency domain impedance with rational function approximation using vector fitting. This paper presents a method of computing the simultaneous switching noise through a switching current, whose properties and details are described. Thus, the results are discussed and performed using MATLAB and PSpice tools. It demonstrated that the presence of many cores in the same PCB influences the SSN due to electromagnetic coupling.

Improvement of Negative Bias Temperature Instability Circuit Reliability and Power Consumption Using Dual Supply Voltage

Improvement of Negative Bias Temperature Instability Circuit Reliability and Power Consumption Using Dual Supply Voltage

An ultra low-power front-end IC for wearable health monitoring system.

This paper presents a low-power front-end IC for wearable health monitoring systems. The IC, designed in a standard 0.13μm CMOS technology, fully integrates a low-noise analog front-end (AFE) to process the weak bio-signals, followed by an analog-to-digital converter (ADC) to digitize the extracted signals. An AC-coupled driving buffer, that interfaces between the AFE and the ADC is introduced to scale down the power supply of the ADC. The power consumption decreases by 50% compared to the case without power supply scaling. The AFE passes signals from 0.5Hz to 280Hz and from 0.7Hz to 160Hz with a simulated input referred noise of 1.6μVrms and achieves a maximum gain of 35dB/41dB respectively, with a noise-efficiency factor (NEF) of the AFE is 1. The 8-bit ADC achieves a simulated 7.96-bit resolution at 10KS/s sampling rate under 0.5V supply voltage. The overall system consumes only 0.86μW at dual supply voltages of 1V (AFE) and 0.5 V (ADC).