A 20 k-to-100kS/s Sub-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>W 9.5b-ENOB Asynchronous SAR ADC for Energy-Harvesting Body Sensor Node SoCs in 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m CMOS

Abstract

This brief presents an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for energy-harvesting body sensor node system-on-chips applications. To improve the power efficiencies of analog and digital blocks independently, a dual-supply voltage scheme is adopted, and a clock-to-Q delay compensator is proposed to realize the timing-calibration-free asynchronous operation with scalable supply voltages. For a maximum sampling rate of 20 kS/s, the SNDR is increased by 3 dB and the power consumption of the SAR logic is decreased by 37%, improving the FoM $_{\text{W}}$ by 26% with the analog and digital supply voltages of 0.6 V and 0.35 V, compared with the single supply of 0.4 V. To obtain a high effective number of bits (ENOB), the ADC exploits a current-biased dynamic comparator and a capacitive DAC with a modified partial common-centroid layout. With a DNL of +0.18/−0.2 LSB and an INL of +0.26/−0.25 LSB, the ADC achieves an ENOB of 9.64 bits at a sampling rate of 100 kS/s, exhibiting power consumption of 562 nW. The prototype ADC is fabricated in 0.18- ${\mu }\text{m}$ CMOS technology, occupying an area of 0.0468 mm2.