Dual-rail Circuits Research Articles

A power constant logic circuit based on mask control

As the structure of existing anti-power attack circuits has certain security problems, this paper proposes a new mask-based control constant power logic circuit based on the existing masking technology. By integrating OR/NOR and AND/NAND circuits into a dual-rail circuit, different circuit logic functions can be controlled by inputting different masks. By introducing two parameters, Normalised Energy Deviation (NED) and Normalised Standard Deviation (NSD), the structure proposed in this paper improves the level of resistance of the circuit to power attacks to a certain extent, as well as reduces the cost of the circuit compared to other power attack resistant circuits.

Odd Judgment Circuit of Four Inputs Based on DNA Strand Displacement

In the development of electronic technology integrated circuits, researchers focus on new calculation methods and new calculation models. The alternative technology of DNA strands is the rapid development of existed biotechnological methods for calculating new types of faster growth. In addition, a new idea for the odd judgment logic circuit based on DNA strand displacement reaction technology is proposed to solve practical problems in mathematics, and which is widely used for those various logic circuits and computing systems to acquire important roles in biological computers. The operational design of the decision circuit is also essential for the logical computing of biological computers. The odd-numbered decision circuit represents the input and output signals during the design process, and that is designed to have the number of single-chain structures of four input signals and one output signal. Finally, the molecular logic circuit is formed by using a primary seesaw circuit. From the simulation results about the dual-rail logic circuit design and the present invention, the idea of using an alternative technology is derived, and the logic circuit deserves a very reliable design. It is a good technical support and a good theoretical basis provided for the future development of biological computers through the odd judgment logic circuit.

Pattern Recognition of 2 × 2 Matrices Based on DNA Strand Displacement

Biochemical circuits have been transformed from simple logic circuits to large-scale complex circuits, benefitting from the maturity of DNA strand displacement technology. Pattern recognition is a process of analyzing perceptual signals and identifying and interpreting objects. In this study, pattern recognition of 2 × 2 matrices based on DNA strand displacement was designed, including dual-rail circuits and seesaw circuits. The effective results were obtained by simulation in Visual DSD software, simultaneously, the pattern recognition and DNA strand displacement technology were perfectly combined.

Self-timed, minimum latency circuits for the internet of things

This work presents a design flow for asynchronous, self-timed dual-rail circuits which introduces a timing assumption in the return-to-spacer phase. The design flow enables power proportionality and is demonstrated through the design of a 32-bit ripple-carry adder and a 32-bit comparator for internet of things applications. The designs are synthesized to a 65 nm cell library with state-of-the-art transistor sizing for subthreshold. Simulation results show improved performance and energy per computation across operating conditions compared with single-rail equivalents. The design flow allows extension of the power proportional philosophy to a wider range of circuits.

Paired T‐element design for multiple‐state acknowledge dependency

A paired T-element that assists in successfully controlling a dual-rail delay-insensitive asynchronous circuit system that implements multiple states containing acknowledge networks, that are interdependent, is presented. A T-element allows triggering of next-state actions concurrently with negation of its acknowledge input. However, this introduces a timing assumption that can cause system failure if it is violated. With little additional overhead, the paired T-element is designed to combine the functionality of two standard T-elements and allow adjacent reads to take place when there are inter-state dependencies. This component successfully overlaps advantages of the performance optimisation of the original T-element with the safety of the solution to this control scenario, making it an important element to be used in dual-rail delay-insensitive asynchronous circuit systems.

Single-Rail MOS Current Mode Logic Circuits for Low-Power and High-Speed Applications

Abstract MOS Current-Mode Logic (MCML) is usually used for high-speed applications. However, almost all MCML circuits are realized with dual-rail scheme. The dual-rail logic circuits increase extra area overhead and the complexity of the layout place and route. Moreover, little standard cells of the dualrail logic circuits have been developed for place-and-route tools, such as Cadence Encounter. In this paper, a single-rail scheme of MCML circuits is proposed. The design methods of the basic single-rail MOS Current-Mode Logic (SRMCML) circuits are presented, such as inverter/buffer, OR2/NOR2, AND2/NAND2, OR3/NOR3, and 1-bit full adder. All circuits are simulated with HSPICE at the SMIC 130 nm CMOS process. The power dissipations of the basic SRMCML cells are compared with the conventional dual-rail MCML ones. The power dissipation of the proposed SDMCML circuits is almost the same as the conventional dual-rail ones. The SRMCML circuit can attain smaller powerdelay product than dual-rail MCML ones because of its single-rail scheme.

Robust Two-Phase RZ Asynchronous SoC Interconnects

A novel two-phase RZ delay-insensitive asynchronous handshaking protocol for on-chip communication has been developed along with an efficient and robust dual-rail circuit implementation (Transmitter/Receiver). Performance was verified using SPICE simulations with a 0.13 μm, 1.2 V technology and compared to that of the best-in-class asynchronous transceivers in terms of forward and backward latencies, throughput, energy per bit transfer and design complexity. Results demonstrate the superior overall performance of the new transceiver.

Path switching: a technique to tolerate dual rail routing imbalances

Dual Rail Precharge (DRP) circuits, which are theoretically secure against differential power analysis attacks, suffer from an implementation problem: balancing the routing capacitance of differential signals. To solve this, four proposals have been put forward: Divided Wave Dynamic Differential Logic (DWDDL) (Tiri and Verbauwhede in DATE '04, pp. 246---251, [2004]), FatWire (Tiri and Verbauwhede in Cardis 2004, pp. 143---158, [2004]), Backend Duplication (Guilley et al. in Lecture Notes in Computer Science, vol. 3659, pp. 383---397, [2005]) and Three Phase Dual Rail (Bucci et al. in Lecture Notes in Computer Science, vol. 4249, pp. 232---241, [2006]). Of these, three (DWDDL, FatWire, Backend Duplication) proposals alter the routing mechanism of Standard Place and Route tools, which in turn introduces an additional step. The other proposal introduces a third phase which reduces the system's performance. In this paper we propose a new countermeasure, Path Switching, to address the routing problem in DRP circuits. From SPICE simulations we show that our proposal does not reveal the secret key for up to 300,000 traces, an increase of 75 times over normal Dual Rail circuits and 3000 times over normal single rail circuits.

An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style

In recent years, certain countermeasures against differential power analysis (DPA) at the logic level have been proposed. Recently, Popp and Mangard proposed a new countermeasure-masked dual-rail pre-charge logic (MDPL); this countermeasure combines dual-rail circuits with random masking to improve the wave dynamic differential logic (WDDL). They claimed that it could implement secure circuits using a standard CMOS cell library without special constraints for the place-and-route method because the difference between the loading capacitances of all the pairs of complementary logic gates in MDPL can be compensated for by the random masking. In this paper, we particularly focus on the signal transition of MDPL gates and evaluate the DPA-resistance of MDPL in detail. Our evaluation results reveal that when the input signals have different delay times, leakage occurs in the MDPL as well as WDDL gates, even if MDPL is effective in reducing the leakage caused by the difference in loading capacitances. Furthermore, in order to validate our evaluation, we demonstrate a problem with different input signal delays by conducting measurements for an FPGA.

Security Evaluations of MRSL and DRSL Considering Signal Delays

In recent years, some countermeasures have been proposed against differential power analysis (DPA) at the basic composition element level of logic circuits. We propose a countermeasure named random switching logic (RSL). RSL involves computation with data masking using a single logic gate and suppression of transient transitions using ENABLE signals generated independently of input data. Recently, some countermeasures that were proposed against DPA, such as MRSL and DRSL, adopted the concept of RSL. Although MRSL is based on RSL, it uses a different method to suppress the transient transitions. DRSL uses RSL to avoid the possibility of leakage caused by a difference in delays occurring in MDPL that combines dual-rail circuits with random masking. The important difference between these countermeasures and RSL is that they can vary the output transition timing depending on the input data patterns. In this paper, we focus on this feature to evaluate the DPA resistance of MRSL and DRSL. Experiments are also conducted on DPA resistance by using an FPGA to verify the evaluation results. It is confirmed that in both MRSL and DRSL, there is a possibility of leakage if a sufficient difference in delays exists in input signals.

Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams

We propose a new method of logic synthesis for dual-rail RSFQ (rapid single-flux-quantum) digital circuits. RSFQ circuit technology is one of the strongest candidates for the next generation technology of digital circuits. For representing logic functions, we use a root-shared binary decision diagram (RSBDD) which is a directed acyclic graph constructed from binary decision diagrams. In the method, first we construct an RSBDD from given logic functions, and then reduce the number of nodes in the constructed RSBDD by variable re-ordering. Finally, we synthesize a dual-rail RSFQ circuit from the reduced RSBDD. We have implemented the method and have synthesized benchmark circuits. We have synthesized dual-rail circuits that consist of about 27% fewer logic elements than those synthesized by a Transduction-based method on average.

Design Method of High Performance and Low Power Functional Units Considering Delay Variations

As VLSI technology advances, delay variations will become more serious. Delay-insensitive asynchronous dual-rail circuits tolerate any delay variation, but their energy consumption is more than double that of the single-rail circuits because signal transitions occur every cycle in all bits regardless of the input bit pattern. However, in functional units, a significant number of input bits may not change from the previous input in many cases. In such a situation, calculation of these bits is not required. Thus, we propose a method, called unflip-bits control, makes use of the above situation, to reduce energy consumption. We evaluate the energy consumption and performance penalty for the method using HSPICE and the verilog-XL simulator, and compare the method with the conventional dual-rail circuit and a synchronous circuit. Our evaluation results reveal that the proposed asynchronous dual-rail circuit has a 12--60% lower energy consumption compared with a conventional asynchronous dual-rail circuit.

Design and Analysis of Dual-Rail Circuits for Security Applications

Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the advanced encryption standard (AES) have been simulated and compared in order to evaluate the method and the tool.

Synthesis of Single/Dual-Rail Mixed PTL/Static Logic for Low-Power Applications

We present single- and dual-rail mixed pass-transistor logic (PTL) synthesis method based on genetic search and compared the results with their conventional static CMOS counterparts synthesized using a commercial logic synthesis tool in terms of area, delay, and power in an experimental 0.1- and 0.13-/spl mu/m CMOS technologies as well as a 0.13-/spl mu/m floating-body partially depleted silicon-on-insulator (PDSOI) process. The proposed synthesis method first performs a search for possible matches between a logic structure and a set of predefined PTL/static logic gates using binary decision diagrams (BDDs). The unique contribution of our approach is the use of a genetic algorithm to determine the best mixture of PTL and static cells based on area and power. Our experimental results demonstrate that both single- and dual-rail mixed PTL circuits synthesized using the proposed mixed PTL/CMOS synthesis method outperforms their static counterparts in delay and power in bulk CMOS as well as silicon-on-insulator (SOI) CMOS technologies. The average power of single- and dual-rail mixed PTL/Static ISCAS'85 benchmark circuits using the proposed method in the 0.1-/spl mu/m bulk CMOS process are 73% and 50% better than their static counterparts with performance gains of 5% and 10%, respectively.

Masking the energy behaviour of encryption algorithms

Smart cards are vulnerable to both invasive and noninvasive attacks. Specifically, noninvasive attacks using power and timing measurements to extract the cryptographic key have drawn a lot of negative publicity for smart card usage. The power measurement techniques rely on the data-dependent energy behaviour of the underlying system. Further, power analysis can be used to identify the specific portions of the program being executed to induce timing glitches that may in turn help to bypass key checking. Thus, it is important to mask the energy consumption when executing the encryption algorithms. The instruction set architecture of a simple five-stage pipelined smart card processor with secure instructions to mask the energy differences due to key-related data-dependent computations in DES and Rijndael encryptions is augmented. The secure versions operate on the normal and complementary versions of the operands simultaneously to mask the energy variations due to value-dependent operations. However, this incurs the penalty of increased overall energy consumption in the data-path components. Consequently, we employ secure versions of instructions only for critical operations; that is we use secure instructions selectively, as directed by an optimising compiler. Using a cycle-accurate energy simulator, the effectiveness of this enhancement is demonstrated. The approach achieves energy masking of critical operations, consuming 83% less energy compared to existing approaches employing dual rail circuits.

Hysteresis effect in pass-transistor-based, partially depleted SOI CMOS circuits

This paper presents a detailed study on the hysteretic delay variations of pass-transistor-based circuits with floating-body partially depleted silicon-on-insulator CMOS devices. It is shown that the pass-transistor can be conditioned into a initial state with extremely high body voltage (exceeding the power supply voltage V/sub DD/), thus resulting in highly hysteretic delay variations when the body subsequently loses charges through the switching cycles. Basic physical mechanisms underlying the hysteretic circuit behavior and its frequency dependence are examined. Different initial states of the circuit are shown to cause large delay disparity at the beginning of the switching activity, yet they converge as the circuit approaches steady state. Use of a cross coupled dual-rail circuit configuration is shown to be very effective in reducing the hysteretic delay variation and its frequency dependence.

RSFQ multiplexer and demultiplexer

An 1:8 RSFQ demultiplexer (DEMUX) and an 8:1 RSFQ multiplexer (MUX) were designed, simulated and optimized to operate at about 20 GHz. Both the inputs and outputs of the DEMUX are complementary dual-rail signals. The basic 2-bit DEMUX module is a self-clocked dual-rail T flip-flop. This DEMUX has a simpler structure than an earlier version of a data-driven-self-timed (DDST) DEMUX developed in our laboratory; however its simulated dc bias margin is (-20%, +20%), which is lower than the more complex device (-29%, +29%). The MUX takes lower data rate single-rail inputs and combines them sequentially into a single output. The complementary output is recovered from the output itself to facilitate interfacing to other dual-rail circuits on chip. The calculated dc bias margin is (-30 %, +28%). Circuit functionality is verified for the 2-bit MUX and the 2-bit DEMUX at low speed. An on-chip high-speed test system is designed to evaluate operation of the MUX and DEMUX at 20 GHz. The circuits are fabricated using a 1 kA/cm/sup 2/ niobium process at both UCB and HYPRES.

A dual rail circuits synthesis environment for the implementation of multiple output boolean functions

This paper presents an integrated CAD system for synthesizing high-performance dual rail circuits using DCVS logic. The proposed techniques exploit ROBDDs to provide efficient DCVS trees that fulfill the design rules and constraints. Sharing of common transistor structures is examined to decrease further the overall device count and chip area by improving the wirability of DCVS circuits. This is accomplished by generating a common variable ordering that permits identification of common subcircuits and simplification of routing procedures by enhancing straight-line wiring of input signals. The paper also presents the integration steps that are undertaken for importing the developed tools into Alliance CAD system, in order to provide a complete and consistent DCVS circuits synthesis environment and methodology. Moreover, experimental results showed that the proposed algorithms, which are time and memory efficient, produce near optimal device counts improving placement and routing procedures. The integrated design framework, which is available for academic and research purposes, has been employed to synthesize, simulate and layout a programmable 16-bit serial/parallel multiplier as a complete DCVS circuit synthesis example.

Rapid single-flux-quantum dual-rail logic for asynchronous circuits

Dual-rail logic circuit elements based on rapid single-flux-quantum (RSFQ) technology have been designed and simulated. The proposed circuits can operate asynchronously, since dual-rail data include timing information in themselves. Therefore dual-rail logic scheme has a possibility of solving some problems of RSFQ circuits with flow clocking, which would become more serious as operating speed and complexity of the circuit increase. Implementation of RSFQ dual-rail AND and XOR cells is described. A scheme of transfer-ring data from a flow-clocked circuit to a parallel dual-rail circuit is also proposed, which a fully asynchronous dual-rail demultiplexer.

Skew-tolerant domino circuits

As cycle time of chips shrinks and die size grows, clock skew measured as a fraction of the cycle time is increasing. Traditional domino circuits shown are especially sensitive because skew must be budgeted in both half-cycles. The problem with such domino pipelines is that evaluation starts when the clock connected to the first gate in the half-cycle rises but the output needs to be valid before the clock on the output latch falls. In the worst case, the evaluate clock is late and the latch clock is early, decreasing time for logic. Many designers realize that some of the overhead can be reduced by using differential domino (also called dual rail) designs. An SR latch or pipeline latch at the end of dual-rail circuits lessens sensitivity to the falling edge. Self-timed techniques eliminate clocks and clock skew, but raise new issues of control overhead, timing assumption verification, and testability. The methodology reported here boosts operating frequency by tolerating clock skew, eliminating latches from the critical path, and better balancing logic between phases of the pipeline.