Skew-tolerant domino circuits

Abstract

As cycle time of chips shrinks and die size grows, clock skew measured as a fraction of the cycle time is increasing. Traditional domino circuits shown are especially sensitive because skew must be budgeted in both half-cycles. The problem with such domino pipelines is that evaluation starts when the clock connected to the first gate in the half-cycle rises but the output needs to be valid before the clock on the output latch falls. In the worst case, the evaluate clock is late and the latch clock is early, decreasing time for logic. Many designers realize that some of the overhead can be reduced by using differential domino (also called dual rail) designs. An SR latch or pipeline latch at the end of dual-rail circuits lessens sensitivity to the falling edge. Self-timed techniques eliminate clocks and clock skew, but raise new issues of control overhead, timing assumption verification, and testability. The methodology reported here boosts operating frequency by tolerating clock skew, eliminating latches from the critical path, and better balancing logic between phases of the pipeline.