Single-Rail MOS Current Mode Logic Circuits for Low-Power and High-Speed Applications

Abstract

Abstract MOS Current-Mode Logic (MCML) is usually used for high-speed applications. However, almost all MCML circuits are realized with dual-rail scheme. The dual-rail logic circuits increase extra area overhead and the complexity of the layout place and route. Moreover, little standard cells of the dualrail logic circuits have been developed for place-and-route tools, such as Cadence Encounter. In this paper, a single-rail scheme of MCML circuits is proposed. The design methods of the basic single-rail MOS Current-Mode Logic (SRMCML) circuits are presented, such as inverter/buffer, OR2/NOR2, AND2/NAND2, OR3/NOR3, and 1-bit full adder. All circuits are simulated with HSPICE at the SMIC 130 nm CMOS process. The power dissipations of the basic SRMCML cells are compared with the conventional dual-rail MCML ones. The power dissipation of the proposed SDMCML circuits is almost the same as the conventional dual-rail ones. The SRMCML circuit can attain smaller powerdelay product than dual-rail MCML ones because of its single-rail scheme.