Abstract
Power-efficient designs are essential for micro-power sensor systems. This paper presents a power-gating scheme for MCML (MOS Current Mode Logic) circuits with separable-sizing sleep transistors. In the proposed scheme, two high-threshold power-gating transistors are inserted between load transistors and outputs of the MCML circuits. The widths and lengths of sleep transistors in power-gated blocks are separately adjusted, which are independent of the bias circuit. Basic cells and a 1-bit full adder are used to verify the correctness of the proposed scheme. The power consuming comparisons between conventional MCML and proposed power-gating MCML circuits are carried out. The 1-bit MCML full adder based on the proposed scheme nearly saves 36% of energy dissipations with respect to no-power-gating MCML one, for a power-gating activity of 0.6. Moreover, the proposed power-gating MCML circuit also has a great advantage in power dissipations in high frequency regions compared with the power-gating static CMOS ones. The power consumption of the MCML 1-bit full adder based on the proposed scheme is 63.2%, 44.8%, and 36.97% compared with the powergating static CMOS one when the operating frequency is 1GHz, 1.5GHz, and 2GHz, respectively.
Highlights
INTRODUCTIONEnergy is one of the most important factors in circuit designs. Besides, the importance of energy-efficient becomes greater than before, as the number of micro-power sensor systems and portable computers grow drastically [1]
Nowadays, energy is one of the most important factors in circuit designs
The widths and lengths of sleep transistors in power-gated blocks are separately adjusted, which are independent of the bias circuit
Summary
Energy is one of the most important factors in circuit designs. Besides, the importance of energy-efficient becomes greater than before, as the number of micro-power sensor systems and portable computers grow drastically [1]. Edyn is the dynamic dissipation, Eleakege is the static consuming, CL represents the load capacitance, VDD means the source voltage, Ileakage is the leakage current, and T is the operation cycle, respectively. The power dissipation of MCML circuits is not related to operating frequencies, and the power consumption of MCML circuits is lower than the conventional CMOS ones in high speed applications [7, 8]. Power gating is an effective way to reduce the steady leakage power consuming of static CMOS circuits. Similar to the static CMOS, MCML circuit can be power-gated to reduce the power dissipations in sleep mode. A reduced swing logic style that named as dynamic current mode logic has been put forward [11] It has a bad noise margin with complex structure
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