Abstract
In high-speed applications, MOS current mode logic (MCML) is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP). However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML) circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.
Highlights
High-speed circuits are required in a wide range of applications such as high-speed processors and Gbps multiplexers for optical transceivers [1, 2]
The basic dual-rail MOS current mode logic (DRMCML) buffer/inverter with its biasing circuit is shown in Figure 1, which is composed of three main parts: the PMOS transistors P1 and P2 that are used as load resistors, the evaluation tree with full differential pull-down switch network consisting of N1 and N2, and the biasing current source transistor Ns
Scaling down the supply voltage of single-rail MCML (SRMCML) circuits can effectively reduce their power consumption, because their power dissipation is in direct proportion to the supply voltage
Summary
High-speed circuits are required in a wide range of applications such as high-speed processors and Gbps multiplexers for optical transceivers [1, 2]. The logic evaluation tree of the SRMCML cells such as AND and OR gates can be realized by only using MOS transistors in parallel. This can further reduce power dissipations because of their low source voltage [12]. The analysis model for calculating minimum supply voltage of single-rail MCML (SRMCML) circuits is addressed, so that the minimum supply voltage of SRMCML circuits can be estimated according to the model parameters of MOS transistors. The work of this paper is summarized in the last section
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