Dual-port RAM Research Articles

A Complete Single-Chip GPS Receiver With 1.6-V 24-mW Radio in 0.18-<tex>$mu$</tex>m CMOS

We have developed a complete single-chip GPS receiver using 0.18-/spl mu/m CMOS to meet several important requirements, such as small size, low power, low cost, and high sensitivity for mobile GPS applications. This is the first case in which a radio has been successfully combined with a baseband processor, such as SoC, in a GPS receiver. The GPS chip, with a total size of 6.3 mm /spl times/ 6.3 mm, contains a 2.3 mm /spl times/ 2.0 mm radio part, including RF front end, phase-locked loops, IF functions, and 500 K gates of baseband logic, including mask ROM, SRAM, and dual port SRAM . It is fabricated using 0.18-/spl mu/m CMOS technology with a MIM capacitor and operates from a 1.6-2.0-V power supply. Experimental results show a very low power consumption of, typically, 57 mW for a fully functional chip including baseband, and a high sensitivity of -152dBm. Through countermeasures against substrate coupling noise from the digital part, the high sensitivity was successfully achieved without any external low-noise amplifier.

Measurement Research of Parameter on Three-Dimensional Braided Composite Material Preform Surface

This paper describes a new measuring algorithm for three-dimensional (3-D) braided composite materials preform exterior average braided angle based on image texture. In this project, an advanced nonlinear filtered algorithm for image of 3-D braided composite materials preform was developed. The digital signal processor, TMS320C/F240, has been used as a device for the preform exterior image filtering. The nonlinear filter consisted of minimum, median, and maximum filters. The DUAL PORT RAM, TC514256, has been used as image buffer. The proposed implementations achieve more powerful and stable noise reduction than commercial algorithms. In this research we also propose a more effective and rapid system design method and describe the procedure and how to implement our proposed algorithms by using the surface image testing system. A real time preform surface image collecting and filtering system was developed without PC controlling (the FPGA technology and digital signal process were used). To show the effectiveness of the proposed designing scheme, angular power spectrum algorithms were designed and it generated an optimized and portable code using assemble and VC language; then it was downloaded to a PC. It built programs that helped speed up the system so as to produce high quality results in less time. Experimental results show that the proposed method is feasible. The research was appraised by Science & Technology Committee of Tianjin. The appraisal report shows the research is advanced in the world. So far, the research is a new development for 3-D braided composite material preform measuring. It will provide the perfect data for improving artifact technology for 3-D braided composite material preform.

A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell

First-in-first-out (FIFO) data storages are in great demand for telecommunication LSIs. This paper presents high-speed and low-power CMOS memory techniques specialized for FIFO operation. A size-configurable architecture using the tile methodology is employed to customize the word counts and/or data bits with a. short time of less than 30 min. Four flag bits are introduced to inform the internal state of FIFO memories. To obtain a higher operating speed, an SRAM-like memory cell with current-sense readout is used. The critical-path delay of the Gray-code up/down counter, indicating the stored data volume, is shortened to 6.0 ns (66%) by using a double-rail single-stage XOR circuit. As to the low-power techniques, a wordline/bitline-swapped dual-port memory-cell architecture is proposed to cut off the static power-supply current of unselected columns. By using the hidden blanket-precharged bitline scheme, the power dissipation of the writing circuitry is minimized without degrading the operating speed. A new data-driven gated-shift-pulse architecture is also proposed to reduce the power dissipation of shift-register-type address pointers (1.5 mW at 100 MHz). A 2K-words /spl times/ 8-bits FIFO memory test chip, fabricated with a 0.6-/spl mu/m CMOS process (a short effective channel length of 0.35 /spl mu/m is available for both the nMOS and pMOS), has demonstrated the 140-MHz operation at a typical 3.3-V power supply. The power dissipation in standby is less than 0.1 /spl mu/W and that at 100-MHz dual-port operation with single fan-out loads is in the range from 28 mW (in the best case with the M-scan test pattern) to 46 mW (in the worst case with the checkerboard test pattern).

Efficient tests for realistic faults in dual-port SRAMs

This paper begins with an overview of realistic fault models for dual-port memories, divided into single-port faults and faults unique for dual-port memories. The latter faults cannot be detected with conventional single-port memory tests; they require special tests. A precise notation for all faults, such that ambiguities and misunderstandings are prevented, has been emphasized. Next, the paper presents a methodology to design tests for realistic unique dual-port memory faults, resulting in a set of three linear single-addressing tests which are merged into a single march test (March s2PF), and one linear double-addressing test (March d2PF). March s2PF and March d2PF have been implemented at Intel. The results show that they detect unique faults, i.e., faults that cannot be detected with conventional single-port memory tests. This make them very attractive industrially.

Design of a 3780-point IFFT processor for TDS-OFDM

This correspondence presents a design of 3780-point IFFT processor for TDS-OFDM terrestrial DTV transmitter using FPGA. It demonstrates the algorithm design and error analysis of the processor, which can achieve a throughput of 7.56M complex IFFT operations per second. This design meets the signal-to-quantization noise ratio requirement of the TDS-OFDM system. It consists of two FPGA and one dual-port RAM. The data stream pipeline algorithm is implemented.

High bandwidth on-chip cache design

In this paper, we evaluate the performance of high bandwidth cache organizations employing multiple cache ports, multiple cycle hit times, and cache port efficiency enhancements, such as load all and line buffer, to find the organization that provides the best processor performance. Using a dynamic superscalar processor running realistic benchmarks that include operating system references, we use execution time to measure processor performance. When the cache is limited to a single cache port without enhancements, we find that two cache ports increase processor performance by 25 percent. With the addition of line buffer and load all to a single pelted cache, the processor achieves 91 percent of the performance of the same processor containing a cache with two ports. When the processor is not limited to a single cache port, the results show that a large dual-ported multicycle pipelined SRAM cache with a line buffer maximizes processor performance. A large pipelined cache provides both a low miss rate and a high CPU clock frequency. Dual-porting the cache and using a line buffer provide the bandwidth needed by a dynamic superscalar processor. The line buffer makes the pipelined dual-ported cache the best option by increasing cache port bandwidth and hiding cache latency.

An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications

A low-power multimedia processor for mobile applications is presented. An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphics processing, 2-kB dual-port SRAM, and peripheral blocks are integrated together on a single chip, MPEG-4 SP@L1 video decoding and 3-D graphics rendering with a 16-b depth-buffer alpha-blending double-buffering and gouraud-shading features at 2, 2-Mpolygons/s speed are realized with the help of the dedicated hardware accelerators/ The architecture of the processor is optimized in terms of power consumption and performance, and various low-power circuit techniques are adopted in each hardware block. The chip is implemented using 0.18-/spl mu/m embedded memory logic (EML) technology. Its area is 84 mm/sup 2/, and power consumption is 160 mW when all of the functions are activated.

Data reordering converter: an interface block in a linear chain of processing arrays

This paper addresses the problem of hardware synthesis of data reordering converter intended to reorganize the layout of transferred data between various processing stages (components) with different I/O format requirements. The proposed design is based on two objectives: (a) fixed bandwidth to main memory, and (b) scalability to higher performance without increasing main-memory bandwidth. The data reordering converter involves two address transformators and an array of dual-port RAMs. The use of distributed dual-port RAM architecture provides several benefits. First, to exploits parallelism, second, to achieve very high-speed data transfer, and third, to allow random access to data elements within the stream. We outline a new architecture for interfacing processing stages in a linear chain, which operate in a pipeline-parallel fashion that trades speed advantages of systolic/processor arrays with area advantages of high wire organizations. An implementation, in VLSI, of address transformators is described, and shown why data reordering converter is useful in designing special purpose high-performance computing for embedded digital signal processing applications.

Real time data acquisition with transputers and PowerPCs using the wavelet transform for event detection

In this paper a new data acquisition system for the soft-X-ray diagnostics in a large fusion plasma experiment is described. The main purpose of this system is to provide real time facilities for analyzing the acquired data, to generate necessary information for the dynamical adaptation of sample rates, and to deliver triggers when certain events in the plasma are detected. The hardware is built on a network of up to 72 transputers and up to four modules, each consisting of a PowerPC and a transputer coupled via dual-ported RAM. The transputers are used for collecting the incoming data from ADCs (each sampled with 500 KHz), and for communication and synchronization within the computer network. Four PowerPCs can analyze up to eight selected channels in real time and provide the results to the other transputers in the network. The algorithm running on the PowerPCs is performing a wavelet like time-frequency transform for the detection of plasma events. With this system it was possible to observe high-n/m mode cascades following impurity accumulation. A report on this effect has been published in Physical Review Letters.

Designing high bandwidth on-chip caches

In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization that provides the best processor performance. Processor performance is measured in execution time using a dynamic superscalar processor running realistic benchmarks that include operating system references. The results show that a large dual-ported multi-cycle pipelined SRAM cache with a line buffer maximizes processor performance. A large pipelined cache provides both a low miss rate and a high CPU clock frequency. Dual-porting the cache and the use of a line buffer provide the bandwidth needed by a dynamic superscalar processor. In addition, the line buffer makes the pipelined dual-ported cache the best option by increasing cache port bandwidth and hiding cache latency.

Low power dual-port CMOS SRAM macro design

A novel low power dual-port CMOS SRAM structure is described. The inherent low power advantage is obtained by using current-mode rather than voltage-mode signal transmission. The design of this new dual-port memory cell and current-mode sense amplifier is based on 0.5 µm, 5 V CMOS logic process technology. HSPICE simulations show that the circuits can operate at high speed even if the supply voltage is reduced to 2 V. The dual-port memory cell is most suitable for the design of FIFO buffers.

A 250-MHz skewed-clock pipelined data buffer

A synchronous dual-port memory employing a three-transistor (3T) dynamic cell has been designed for use as a high throughput embedded data buffer in digital switching and signal processing applications. Skewed-clock pipelining is used to achieve operation at frequencies as high as 250 MHz with a low register element count. The 3T cell provides separate read and write access ports while occupying less than half the area of a conventional dual-port SRAM cell. On-chip Hamming error correction coding (ECC) is used to enhance the fault tolerance of the memory, A 25-kb experimental prototype has been integrated in a 0.8-/spl mu/m CMOS technology; it occupies a die area of 3800 /spl mu/m/spl times/1600 /spl mu/m and dissipates 420 mW while operating at 250 MHz.

Real-time implementation of a 8 kbps CELP coder on a DSP pair

A codec uses low cost digital signal processors (DSPs) to implement the codebook excited linear prediction (CELP) algorithm. The flexible architecture provides a platform for implementing a family of CELP codecs. In a specific example, an 8 Kbps CELP codec is partitioned into parallel tasks for real time implementation on dual DSPs with flexible intertask communication, prioritization and synchronization with asynchronous transmit and receive frame timings. The two DSPs are used in a master-slave pair. Each DSP has its own local memory. The DSPs communicate to each other through interrupts. Messages are passed through a dual port RAM. Each dual port RAM has separate sections for command-response and for data.

Hybrid Josephson-CMOS FIFO

We describe the design of a hybrid Josephson-CMOS first-in-first-out memory (FIFO) for communications and signal processing applications. The FIFO takes advantage of high speed Josephson logic and dense CMOS memory. We focus on the low power CMOS ring pointer architecture employing a dual-port CMOS SRAM array and illustrate how a high speed Josephson demultiplexor-multiplexor pair can greatly increase throughput. We describe a novel eight transistor dual-port CMOS SRAM cell with low swing write and current-mode read with an asymmetric SQUID to perform differential current-sensing. Finally, we discuss the peripheral Josephson demultiplexor and multiplexor designed in edge-triggered logic.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Evaluation of sequential-in-random-out memory device

The buffering of data is a potential bottleneck to performance. In general, the buffer can be implemented either by FIFO or dual-port RAM, which are both two-port memory devices. In the Letter a classification of buffers is proposed. According to the classification, a new two-port memory device with the sequential-in-random-out feature is introduced. Simulation results show that 45% time, at most, could be saved, as compared to a FIFO buffer.

A modular integrated robot control system

The Modular Integrated Robot Control System (MIRCS) is a PC-based distributed control system for industrial robots. This system possesses expansibility and flexibility for the strict requirements of computation power and the complicated robot control. A host computer and several server computers constitute the hardware architecture of MIRCS. The host computer communicates with the other server computers in two ways: tight coupling by dual-port RAM and loose coupling by an Ethernet network. The hierarchical software architecture in MIRCS has several modules to make the system flexible and portable.

Multichannel real-time data acquisition system using dual ported FIFO buffers

In contrast to real-time data acquisition systems employing a minicomputer with a real-time multiprogramming operating system, this paper describes the design and development of a high throughput data acquisition system using an IBM compatible PC/AT, high speed sampling A/D converter, and dual ported FIFO RAM buffers, in the MS-DOS environment. Data acquisition software is developed in Turbo Pascal with a few in-line machine language procedures.

Design techniques for high-throughput BiCMOS self-timed SRAMs

Design techniques for a high-throughput BiCMOS self-timed SRAM are described. A new BiCMOS read circuit using a pipelined read architecture and a BiCMOS complementary clocked driver (BCCD) are proposed to reduce the operating cycle time. A 8192*9-b dual-port self-timed SRAM designed using the proposed techniques achieved a clock cycle time of 3.0 ns, that is, a 333-MHz operating frequency, by SPICE simulation on model parameters for 0.8- mu m BiCMOS technology. A high-speed built-in self-test (BIST) circuit was studied and designed for the 3.0-ns cycle SRAM. It is confirmed that the BIST circuit allows the 3.0-ns cycle SRAM to test at its maximum operating frequency. >

A PC add-on card for Mössbauer data acquisition system

A user friendly Mössbauer data acquisition add-on card for IBM compatible PC has been designed and fabricated. It is a firmware which acquires data and shares the CPU of the host PC to transfer the data into the PC memory. The card generates the wave form for the drive unit, generates dwell time marker pulses and counts the energy selected single channel analyzer (SCA) pulses. The significant feature of the system is that the counting of the SCA pulses is done with two counters, resulting in zero dead time. Two temporary dual port RAMs (DP RAM) on board enable real time data acquisition. The software which controls the hardware is menu driven and user friendly and works under DOS environment. An on line display of the spectrum is provided with a cursor which enables the inspection of counts in any channel during the acquisition. The current version of the spectrometer has a capacity of 2048 channels and this can be extended easily up to 8192 channels.

Modula-2 based multitasking environment for a flexible biprocessor controller

This paper presents the most important issues of a real-time software package developed for the industrial multiloop controller MMC-90. MMC-90 is a biprocessor system based on the concept of a two-level controller. On the lower level of complexity, the base control processor performs the basic control functions. On the higher level of complexity, the flexible control coprocessor executes complex functions on request from the control tasks on the base control processor. All the software on the control coprocessor is written in Modula-2. The corresponding multitasking environment was designed as a set of Modula-2 libraries at various horizontal and vertical decomposition levels. On the control coprocessor a preemptive, priority based scheduler as well as a high level interprocess communication and synchronization mechanism has been developed. Communication between the processors is realized by means of a fast bi-directional communication channel, which is implemented via dual-port RAM. The developed system opens the door to applications of modern control algorithms in industrial practice.