Dual-port RAM Research Articles

Twin Channel of Speed Control System Based on DSP

A microprocessor as the core of the digital controller has become one of the major features AC speed regulation system in modern. Based on DSP as the core of the speed control system，it can realize complex algorithm. At the same time, it can achieve the diagnosis of system’s fault, and the self-setting of parameters controlled, etc. Thus it can make the motor speed control system have higher performance. This paper introduces the motor speed control system which consists of three DSP. This system is able to adjust two Frequency conversion motor. Division of work to the DSP is according to the function of DSP. Inter-DSP makes use of dual-port RAM to exchange data and communicate. They work together to achieve and improve the performance of the control system.

The Design of Embedded AeroEngine Measurement and Test System Based on ARM and FPGA

Present Measurement and test system for aeroengine rig testing is primarily based on DSP and PC104 industrial computer, which have the disadvantages of large volume, high power consumption, single function and less-generic. So it is a valuable job to promote the performance of the system employing the latest methods of collaborative design and embedded hardware and software technology. For designing of the new type improved aeroengine test system, a hardware and software co-design strategy is employed. After a thorough trade-off analysis and comparison among different hardware and software systems, an embedded aeroengine test system based on ARM and FPGA is designed, by using S3C2440A CPU with ARM920T core and FPGA from Xilinx as fundamental hardware data acquisition and process platform, using Linux as real time operating system. The data transmission between ARM and FPGA take the path of dual-port RAM, during which the read-write operation is coordinated by means of interruption. The system uses U-Boot to initialize hardware and load operating system. FPGA is used as foreside of data acquisition system, which sampling parameter setting is loaded by reading configuration file during start-up and read into inner register by SPI bus. Data is exported from flash-chip of test system by means of U-disk or network, and analyzed in PC equipped with specialized software. Strong post-proceeding capacity for multi parameters of aeroengine rig testing can be realized, especially for dynamic signal analysis in time domain, frequency domain. Because of the use of the new platform, a big promotion has been achieved. I) the capacity of data processing increases by 15%. II) The new system allows numbers of the sampling channels to double. III) Abundant functions of software can realize more professional, intelligent and generic tests. IV) Sampling frequencies increases by 20%, meeting the demand of monitoring dynamic random signals such as noise and vibration, on fluctuating pressure with wide frequency band. The embedded aeroengine test system based on ARM and FPGA is successful and the prototype is manufactured and tested. It is found that the performance of the new system is promoted significantly, which shows the effectiveness and reliability of the method employed.

An Interface Design of Communication between PC104 and DSP Based on Dual-Port RAM

This paper focus on a motion control card based on DSP, designed an interface communication between DSP and industrial PC. After a contrast about several methods of communication, this interface take the Dual-port RAM as the final way. This communication method regard the DRAM as the sharing storage unit, use the semaphores of the DRAM chip to prevent visiting the same address at same time on boths port and achieve the high speed communication between DSP and PC104.

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues

Showing that the worst minimum operating voltage (Vmin) of an 8T dual-port (DP) SRAM is determined by the write/read-disturbing condition with a finite clock skew, we propose a circuit technique to detect the worst Vmin in asynchronous clock operation. This circuitry allows us to screen the worst bit in an array that is conventionally obtained by a costly and time-consuming test procedure. For instance, we can at least realize 400x speed-up for the test time compared to the conventional method. We designed and fabricated a 512-kb DP-SRAM macro using 28-nm low-power CMOS technology, and confirmed experimentally that the worst Vmin can be successfully reproduced within 6% discrepancy by our proposed circuit.

Trigger Board for the Auger Surface Detector With 100 MHz Sampling and Discrete Cosine Transform

The surface detector array of the Pierre Auger Observatory contains 1600 water Cherenkov detectors spread over an area of 3000 km <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The Cherenkov light is detected by three 9-inch photomultiplier tubes from which the signals of the anode and last dynode are digitized by 10 bit ADCs. The currently used Front-End Boards equipped with the ACEX <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> and Cyclone <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> FPGA are sampled with 40 MHz. New requirements from the Auger North (100 MHz) and AMIGA (80 MHz) specification as well as the proposal of new spectral triggers based on the 16-point Discrete Cosine Transform (DCT) impose a new Front End Boards with more powerful FPGA chip with a sufficient amount of DSP blocks. The DCT trigger allows recognition of ADC traces with a very short rise time and fast exponential attenuation related to a narrow, flat muon component of very inclined extensive air showers generated by hadrons and starting their development early in the atmosphere. Ten prototype boards equipped with Altera <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> Cyclone <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> III FPGA have been fabricated and successively tested in the lab and in real pampas conditions in six test surface detectors within April 19 - July 26, 2009. Boards contain only a single FPGA chip, which implements also the slow channel, in previous three generations supported by the external Dual-Port RAM. Tests confirmed full stability and high reliability of the digital part. Both lab and field tests confirm a high efficiency of the recognition of expected patterns of ADC traces.

FPGA Implementation of Laplacian of Gaussian Edge Detection Algorithm

This paper introduces a design of gaussian Laplace edge detection algorithm model based on system generator which can be realized in FPGA.The data of a two- dimensional image was changed into a one-dimensional array，before line buffering in two Dual port RAM,the convolution of the image pixel data and the LOG template was carried out in the modules constituted of the component elements such as AddSub, Shift and Delay . After getting the absolute value with the modules of Slice，Negate and Mux ，the output was the image after edge-detection .The module function and the selecting principle was analyzed from the point of view of saving FPGA resources.The WaveScope and resource estimator showed that ：not only the detection result and the running speed was guaranteed but also the FPGA resources can be saved .

FPGA based Reconfigurable 2D FFT System

This paper develops a system level architecture for implementing a cost-efficient, FPGA-based reconfigurable two dimensional (2D) FFT system. The adopted approach considers both the hardware cost (in terms of FPGA resource requirements), and performance (in terms of throughput). These two extremes are optimized based on using run time reconfiguration, double buffering technique, shared Dual Ported RAM (DPRAM) modules and the “hardware virtualization” to reuse the available processing components. The system employs two one Dimensional (1D) FFT processor each with sixteen reconfigurable parallel FFT cores. Each core represents a 16 complex point parallel FFT engine. Thus the architecture supports transform length of 256X256 complex points, as a demonstrator to the design idea, using fixed-point arithmetic and has been developed using radix-4 butterfly architecture. The simulation results that have been performed using VHDL modeling language and ModelSim software shows that the full design can be implemented using single FPGA platform requiring about 50,000 Slices. Keywords: 2D Fast Fourier Transform Radix-4. Run Time Reconfiguration

An Improved Realization of the Digital Multiplexer Based on Electric Power Carrier Communication

The electric power carrier communication is the special communicated way of electrical power system , one kind of double CPU, the low power loss, the low cost digital multiplexer has been designed in conducted the full research to this communicated way, which is satisfied the need of the electric power correspondence transmission system. In respect of hardware designing, dual-port RAM and double CPU are adopted for coordinating work and greatly improving efficiency; dual-port RAM , which functions as a shared mailbox of double CPU, is used to store markers, pointer and coordinate the work of double CPU.

NMEA 2000 프로토콜을 적용한 선박 전력 컨버터 모니터링 시스템에 관한 연구

In this paper, the FPGA-based SoC board (Xilinx Virtex-4 ML401 EVM) is adopted to control electrical power inverter system. For marine application, its performance is shown on PC-based system for monitoring electrical characteristics of a power inverter using by the NMEA 2000 protocol. This power inverter system is achieved in Real-Time monitoring and control by dual micro-processor operation on embedded FPGA-based SoC board. One micro processor is for control (Control processor) electrical power inverter using by PWM signal. And the other microprocessor (Communication processor) is for communication with PC-based monitoring system. The two-processor is communicating each other using by dual-port ram (DPRAM). PC-based system user can control and monitor information of the electrical power inverter via NMEA 2000 based communication processor. Control and monitoring information includes the inverter status and configuration. SoC board converts this information to Parameter Group Numbers (PGNs) in the NMEA 2000 protocol. This system can be applied to marine power electronics for distributed power generation, transmission or regulation systems on the ship.

Central Processing Units for PLC implementation in Virtex-4 FPGA

AbstractThe paper presents an approach to the design and construction of central processing units for programmable logic controllers implemented in a FPGA development platform. Presented units are optimised for minimum response- and throughput time. The CPU structure is based on bit-word architecture and two types of control data exchange methods: with handshaking – control data are passed through the two flip-flop units with acknowledgement; without handshaking – control data are passed through the dual port RAM. Third unit – simple one processor – built to compare with the above two. The paper presents specific timers/counters hardware construction solution. Additionally it presents implementation results which show how many FPGA circuit resources are used to implement presented units.

Design Choice in 45-nm Dual-Port SRAM — 8T, 10T Single End, and 10T Differential

As process technology is scaled down, a large-capacity SRAM will be used. Its power must be lowered. The Vth variation of the deep-submicron process affects the SRAM operation and its power. This paper compares the macro area, readout power, and operating frequency among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM considering the multi-media applications. The 8T SRAM has the lowest transistor count, and is the most area efficient. However, the readout power becomes large and the access time increases because of peripheral circuits. The 10T single-end SRAM, in which a dedicated inverter and transmission gate are appended as a single-end read port, can reduce the readout power by 74%. The operating frequency is improved by 195%, over the 8T SRAM. However, the 10T differential SRAM can operate fastest (256% faster than the 8T SRAM) because its small differential voltage of 50mV achieves high-speed operation. In terms of the power efficiency, however, the readout current is affected by the Vth variation and the timing of sense cannot be optimized singularly among all memory cells in a 45-nm technology. The readout power remains 34% lower than that of the 8T SRAM (33% higher than the 10T single-end SRAM); even its operating voltage is the lowest of the three. The 10T single-end SRAM always consumes less readout power than the 8T or 10T differential SRAM.

Using Data Contention in Dual-ported Memories for Security Applications

Field Programmable Gate Arrays (FPGA) provide the invaluable feature of dynamic hardware reconfiguration by loading configuration bit files. However, this flexibility also opens up the threat of theft of Intellectual Property (IP) since these configuration files can be easily extracted and cloned. In this context, the ability to bind an application configuration to a specific device is an important step to prevent product counterfeiting. Furthermore, such a technology can also enable advanced business models such as device-specific feature activation. In this work, we present a new technique to generate entropy on FPGA device--based on data contention in the hardware circuitry. For this entropy, we use the output of intentionally generated write collisions in synchronous dual-ported block RAMs (BRAM). We show that the parts of this output generated by such write collisions can be either probabilistic but also deterministic and device-specific. The characteristics of such an entropy source can be used for a large variety of security applications, such as chip identification and device authentication. In addition to that, we also propose a solution to efficiently create cryptographic keys on-chip at runtime. As a last contribution, we eventually present a strategy how to transform this entropy source into a circuit for True Random Number Generation (TRNG).

Single Event Upset and Multiple Cell Upset Modeling in Commercial Bulk 65-nm CMOS SRAMs and Flip-Flops

A proprietary Monte-Carlo simulation code dedicated to heavy ion cross-section prediction has been developed. The code is based on diffusion-collection equations, takes into account recombination processes, uses an improved drain strike model, and includes new upset analysis algorithms for different circuit architectures. Simulated cross-sections are compared to heavy ion experimental characterizations for commercial bulk 65-nm single- and dual-port SRAMs. Simulation capabilities of much more complex circuits are demonstrated considering a 65-nm radiation-hardened-by-design (RHBD) Flip-Flop (FF).

Estimation of Heavy-Ion LET Thresholds in Advanced SOI IC Technologies From Two-Photon Absorption Laser Measurements

The laser energy thresholds for SEU for SOI 1-Mbit SRAMs built in Sandia's 0.35-μm SOI technology were measured using carrier generation by two-photon absorption. The laser measurements were correlated to heavy-ion threshold LET measurements to determine an empirical relationship between laser energy threshold and heavy-ion threshold LET. This empirical relationship was used to estimate the threshold LETs for other circuits built in Sandia's 0.35-μm SOI technology and SRAMs built in IBM's 45 and 65-nm SOI technologies. For an ASIC built in Sandia's 0.35-μm SOI technology the estimated threshold from laser measurements was close to the measured heavy-ion threshold LET. However, for a dual-port SRAM also built in Sandia's 0.35-μm SOI technology and for the 45- and 65-nm IBM SOI SRAMs, the threshold LETs estimated from laser measurements did not correlate to the measured heavy-ion threshold LETs. For the IBM SRAMs, the likely cause of the discrepancy between the threshold LETs estimated from laser measurements and the threshold LETs measured by heavy-ion testing is due to the laser pulse simultaneously injecting charge into multiple transistors within a memory cell and/or in adjacent memory cells. This is due to the relatively large size of the laser spot size compared to the size of the SEU sensitive volume of the IBM SOI devices. The hardness assurance implications of these results are discussed.

Memory-Efficient and High-Performance Two-Dimensional Discrete Wavelet Transform Architecture Based on Decomposed Lifting Algorithm

The line-based method has been one of the most commonly-used methods of hardware implementation of two-dimensional (2D) discrete wavelet transform (DWT). However, data buffer is required between the row DWT processor and the column DWT processor to solve the data flow mismatch, which increases the on-chip memory size and the output latency. Since the incompatible data flow is induced from the intrinsic property of adopted lifting-based algorithm, a decomposed lifting algorithm (DLA) is presented by rearranging the data path of lifting steps to ensure that image data is processed in raster scan manner in row processor and column processor. Theoretical analysis indicates that the precision issue of DLA outperforms other lifting-based algorithms in terms of round-off noise and internal word-length. A memory-efficient and high-performance line-based architecture is proposed based on DLA without the implementation of data buffer. For an N × M image, only 2N internal memory is required for 5/3 filter and 4N of that is required for 9/7 filter to perform 2D DWT, where N and M indicate the width and height of an image. Compared with related 2D DWT architectures, the size of on-chip memory is reduced significantly under the same arithmetic cost, memory bandwidth and timing constraint. This design was implemented in SMIC 0.18µm CMOS logic fabrication with 32kbits dual-port RAM and 20K equivalent 2-input NAND gates in a 1.00mm × 1.00mm die, which can process 512 × 512 image under 100MHz.

A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC

This paper describes the design and VLSI implementation of a highly efficient, single-port SRAM-based deblocking filter. It can achieve 204 cycles/macroblock throughput for H.264/AVC real-time decoding. Several deblocking filter designs in the literature have been compared and the possibility of realizing them in a pipeline is studied. Eventually we came up with a completely new design which has a five-stage pipeline with gated clock to increase system throughput while reducing power. Data hazards and structure hazards, which are the two most critical issues for a pipelined filter, are analyzed and resolved. Efficient memory organization for both on-chip SRAM and transposition buffers is employed. By using innovative hybrid edge filtering sequence and out-of-order memory update scenario, we obtain zero stall cycle in normal pipeline flow, making the best out of a pipelined architecture. Compared with existing designs, our design achieves at least 18% clock cycle reduction, as well as 20% lower power consumption owing to its efficient pipeline and memory architecture. The total gate count is comparable to other designs in literature without using any expensive two-port or dual-port on-chip SRAMs.

Extended Kalman Filter based loosely coupled INS/GPS integration scheme using FPGA and DSP

GPS provides an accurate position and velocity information but with a slower update rate, whereas INS provides position, velocity and attitude information with a higher update rate. However, INS alone cannot provide proper solutions due to the increasing error characteristics of the accelerometer and gyros of the inertial sensor. To get an accurate navigation solution, it is necessary to integrate INS with GPS. This paper discusses integration of INS/GPS systems using Extended Kalman Filter (EKF). TMS320vc33 floating point DSP is used for INS and EKF computations. A FPGA (Field Programmable Gate Array) based GPS data acquisition system and Dual Port RAM (DPRAM) have been designed and used for the presented architecture.

Multiple-Bit Upset Analysis in 90 nm SRAMs: Heavy Ions Testing and 3D Simulations

SEU and MBU cross-sections are measured with heavy ions for commercial 90 nm single port and dual port SRAMs. SEU and MBU rates are discussed as a function of the LET and beam tilt. A new sensitive area devoted to MBU is computed with full 3D TCAD simulations on single and adjacent memory cells.

An Efficient Architecture of High-Performance Deblocking Filter for H.264/AVC

We devised an efficient architecture of deblocking filter and implemented the circuit with 15,400 logic gates and a 160×32 dual-port SRAM using 0.25 μm standard cell technology. This circuit can process 88 image frames with 1,280 × 720 pixels per second at 166 MHz. Our circuit requires smaller number of accesses to the external memory than other approaches and hence causes less bus traffic in the SoC design platform.

Scalable ATM network interface design using parallel RISC processors architecture

In this work, a high-speed scalable ATM network interface has been designed and simulated. The interface has two processing engines, one for the transmission and the other for receiving side. Two specialized single-issue RISC cores supported with three stages pipeline and forwarding engine, have been used to process the network interface functions and ATM protocols. In addition, the interface architecture has Content Addressable Memory, five First-In-First-Out buffers, two simple Direct Memory Access units, two dual-port RAM, host interface, and transmission lines interface. The performance evaluation of the network interface has been measured through the development of a VHDL-based cycle accurate simulator. The results have shown that such network interface is scalable and could support a wire-speed of 2.4 Gb/s when the RISC cores run at a clock rate of about 170 MHz.