Abstract
We devised an efficient architecture of deblocking filter and implemented the circuit with 15,400 logic gates and a 160×32 dual-port SRAM using 0.25 μm standard cell technology. This circuit can process 88 image frames with 1,280 × 720 pixels per second at 166 MHz. Our circuit requires smaller number of accesses to the external memory than other approaches and hence causes less bus traffic in the SoC design platform.
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