A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues

Abstract

Showing that the worst minimum operating voltage (Vmin) of an 8T dual-port (DP) SRAM is determined by the write/read-disturbing condition with a finite clock skew, we propose a circuit technique to detect the worst Vmin in asynchronous clock operation. This circuitry allows us to screen the worst bit in an array that is conventionally obtained by a costly and time-consuming test procedure. For instance, we can at least realize 400x speed-up for the test time compared to the conventional method. We designed and fabricated a 512-kb DP-SRAM macro using 28-nm low-power CMOS technology, and confirmed experimentally that the worst Vmin can be successfully reproduced within 6% discrepancy by our proposed circuit.