A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry

Abstract

We propose pseudo dual-port (DP) SRAM by using 6T single-port (SP) SRAM bitcell with double pumping circuitry, which enables 2-read/write (2RW) operation within a clock cycle. The data sequencer for address/data latch and double output sense amplifier realize the simulations read-read or write-write operation. We designed and implemented a 512-kb pseudo DP SRAM macro based on 28-nm low-power bulk CMOS technology. Our design achieved the bit density of 5.92 Mb/mm2, which is the highest ever reported. Measured data at 1.0 V supply voltage shows 1.05 ns read-access-time for one port and 2.37 ns for another port, respectively. Area overhead of the proposed circuitry is only 3.2% compared to the original SP SRAM macro.