Dual Phase-locked Loop Research Articles

Analysis and Implementation of a Frequency Synthesizer Based on Dual Phase-Locked Loops in Cesium Atomic Clock

The frequency synthesizer plays a crucial role in atomic clock technology. In this study, we demonstrate a direct microwave frequency synthesizer for a cesium atomic clock, employing frequency multiplication and a dual-phase-locked loop mode. A mathematical model of the frequency synthesis chain is established to estimate its performance. The phase-settling time and system stability are analyzed and studied in detail, and the obtained results are verified by experiments. An optimized realization of the frequency synthesizer shows that the phase-settling time can be adjusted within the range of 644.5 µs to 1.5 ms. Additionally, we measure the absolute phase noise values to be −63.7 dBc/Hz, −75.7 dBc/Hz, −107.1 dBc/Hz, and −122.5 dBc/Hz at 1 Hz, 10 Hz, 1 kHz, and 10 kHz offset frequencies, respectively.

Position Estimation Accuracy Improvement for SPMSM Sensorless Drives by Adaptive Complex-Coefficient Filter and DPLL

This paper presents an improved high-frequency pulsating square-wave signal injection-based sensorless control for surface-mounted permanent-magnet synchronous machines (SPMSM). The use of low pass filter in the traditional sensorless method results in phase delay and, consequently, degrades the dynamic behavior. In order to eliminate such drawback, the proposed method adopts an adaptive complex-coefficient filter (ACCF) that does not cause phase delay and the use of compensation technique is avoided. Moreover, a dual-phase-locked loop (DPLL) is utilized to extract the accurate rotor position and eliminates the position estimation error in dynamic state. The small signal model of ACCF is build, and then the unified parameter selection guideline for both ACCF and DPLL is given in terms of comprehensive transfer function analysis. The proposed method has been carried out by both simulation and experiment, where a Higale platform with a 0.2-kW SPMSM is adopted to verify the performance of proposed method.

Adaptive Sliding Mode Observer-Based Sensorless Control for SPMSM Employing a Dual-PLL

In order to get rid of the chattering problem of a sliding mode observer, this article presents an adaptive sliding mode observer (ASMO)-based sensorless control for surface-mounted permanent-magnet synchronous machines (SPMSMs). In the conventional sliding mode observer, a large gain is required to ensure the sliding motion stability. However, it leads to undesired chattering and degrades the position estimation accuracy. With the proposed ASMO strategy, the observer gain can be dynamically adjusted according to the back electromotive force (EMF), and it is applicable in wide speed range with improved estimation accuracy. Then, a dual-phase-locked loop (DPLL) is improved to extract accurate rotor position information under dynamic process in both positive and negative rotating directions of the SPMSM. Finally, the effectiveness of the proposed method has been verified by simulation and experiment on a Higale platform with a 0.2-kW SPMSM.

Ultrastable Long-Haul Fiber-Optic Radio Frequency Transfer Based on Dual-PLL

In this paper, we demonstrate ultrastable radio-frequency (RF) transfer over long-haul optical fiber link. Our stabilized RF transfer technique is based on high-performance dual phase locked loops (dual-PLL) configuration which improves signal to noise ratio (SNR) of the round trip transmitted signals. At the local site, the frequency conversion phase-lock receiver (FCPLR) accomplishes high-quality phase tracking of the RF signal which is transmitted after long distance optical fiber link. The low phase noise signal generated by FCPLR is passively mixed with a local reference signal to realize phase conjugation. Through advisable frequency design, there is no residual RF leakage and nonlinear effect of frequency mixing. Another PLL incorporating a high-quality cleanup oscillator is located at the remote site that favourably improves short-term instability of our transmission system. In our experiment, stabilized 2.4 GHz RF signal transfer over a 1007 km optical fiber link is demonstrated without any electric relay system, and the transmission system achieves a fractional frequency instability of 8.20 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-14</sup> @1 sand 7.87 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-17</sup> @10 000 s.

Dual Phase-Locked Loop-Based Speed Estimation Scheme for Sensorless Vector Control of Linear Induction Motor Drives

In power electronics and power systems, the dual-phase-locked loop (DPLL) is a well-accepted approach to maintain zero steady-state errors when subjecting to a frequency ramp input. This distinctive characteristic of the DPLL may make it as a promising candidate for speed estimation in speed-sensorless drive systems. Considering this issue, a DPLL-based speed estimation scheme for linear induction motor speed-sensorless drive systems is presented in this article to achieve accurate speed estimation. The basics of the DPLL and the direct application of the DPLL scheme are provided. However, in practice, the direct application of the DPLL scheme may degrade the performance of the entire system, which includes the nonidealities in the secondary electromotive force (EMF) signals, such as harmonics and parameter variations. Accordingly, the prefilter and the amplitude normalization scheme are employed to mitigate the effect of nonidealities. Meanwhile, the small-signal model of the proposed DPLL scheme is presented, enabling the analysis of the dynamic performance and the comparison of the synchronous reference frame phase locked-loop scheme. In addition, a parameter tuning guideline of the proposed DPLL scheme is detailed by using the derived small signal model. The performance of the proposed DPLL scheme is investigated by experimental tests.

High-Performance Selective and Output Filter Techniques for Sensorless Direct Position and Speed Estimation

This article introduces high-performance filter techniques for direct position and speed estimation to augment its robustness against disturbances. The direct estimation concept provides an independent position and speed estimate at each sampling instant by solving an optimization problem parameterized with the current, current derivative, and voltage of the same sample. It can operate at any speed employing a voltage injection at low speed or pulsewidth modulated current derivative. A selective filter concept is proposed that discards samples lacking robustness based on cost function properties. The concept is most effective in removing worst case errors and should always be applied. Also, output filter techniques are investigated to improve the estimates. A finite impulse response (FIR) structure is proposed that filters estimates according to a least-square criterion and is effective in reducing average estimation errors. The FIR filter is benchmarked against an enhanced dual phase-locked loop (PLL) filter, which is enabled by direct estimation. The FIR and dual-PLL filters are found to have a 6.8 and 1 kHz practical bandwidth, respectively, while achieving a $ 1% absolute mean position and speed estimation error. Hence, they perform one to two orders of magnitude better than traditional estimation schemes, which typically achieve $ 100 Hz bandwidth at similar errors.

Self-Contained High-SNR Underwater Acoustic Signal Acquisition Node and Synchronization Sampling Method for Multiple Distributed Nodes.

Aiming at the application demand in underwater noise monitoring, observation of marine animal, antisubmarine and underwater target localization, a high-SNR underwater acoustic signal acquisition (UASA) node that combines a self-contained acquisition system and floating platform is designed to improve the acquisition performance of a single UASA node, and a high-accuracy synchronization sampling method among multiple distributed UASA nodes based on master-slave dual phase-locked loops (MSDPLL) is proposed to improve the synchronization sampling accuracy. According to the equivalent model of hydrophone and application requirements, low noise signal conditioning circuit and large-capacity data storage modules are designed. Based on the long-term monitoring requirements for underwater acoustic signal and distributed positioning requirements for underwater targets, the structure of a single UASA node is designed and MSDPLL is developed for high-accuracy synchronization sampling among multiple UASA nodes. Related experimental results verified the performance of the UASA node and the synchronization sampling method.

Improving the Accuracy of an Absolute Magnetic Encoder by Using Harmonic Rejection and a Dual-Phase-Locked Loop

This paper proposes a method to improve the accuracy of an absolute magnetic encoder by using harmonic rejection (HR) and a dual-phase-locked loop (DPLL). The encoder consists of two permanent magnets: an edge-located multipolar magnet (MPM) and a center-located bipolar magnet, in which the signal-processing accuracy of the MPM is crucial for achieving high accuracy of the entire encoder. However, the MPM signals are disturbed by nonidealities such as dc offsets, amplitude mismatch, low- and high-order harmonics, and random noises. In this paper, the HR approach investigates the characteristics of nonidealities of the phase detector and rejects them by using gradient descent. In addition, the DPLL remains robust by maintaining a zero steady-state error during a phase jump, a constant frequency, and a ramp frequency. The proposed method is simulated with MATLAB software and implemented in ARM STM32F407ZG. The obtained results demonstrate efficient performance. This method can be applied to any use of quadrature sinusoidal signals, such as in power grids and in permanent-magnet synchronous motor phase detection.

New Configuration of a PLDRO with an Interconnected Dual PLL Structure for K-Band Application

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

Electro-mechanical hybrid PLL for MEMS oscillator temperature compensation system

This paper describes the design and measurement of a dual Phase-Locked Loop system that utilizes a MEMS VCO with a DC-controlled silicon resonator as the frequency-setting element. System-level considerations are given for the use of such structure in temperature compensation system for MEMS reference oscillators. Micromachining process and circuit design challenges of the particular implementation are also discussed. The PLL has been implemented using a 0.35 μm CMOS process and operates with a nominal supply of 3 V. The nominal supply voltage for the MEMS VCO is 24 V with 15 V bias applied to the silicon resonator.

Automated high-throughput viscosity and density sensor using nanomechanical resonators

Most methods used to determine the viscosity and mass density of liquids have two major drawbacks: relatively high sample consumption (∼milliliters) and long measurement time (∼minutes). Resonant nanomechanical cantilevers promise to overcome these limitations. Although sample consumption has already been significantly reduced, the time resolution was rarely addressed to date. We present a method to decrease the time and user interaction required for such measurements. It features (i) a droplet-generating automatic sampler using fluorinated oil to separate microliter sample plugs, (ii) a PDMS-based microfluidic measurement cell containing the resonant microcantilever sensors driven by photothermal excitation, (iii) dual phase-locked loop frequency tracking of a higher-mode resonance to achieve millisecond time resolution, and (iv) signal processing to extract the resonance parameters, namely the eigenfrequency and quality factor. The principle was validated by screening series of 3μL droplets of glycerol solutions separated by fluorinated oil at a rate of ∼6s per sample. An analytical hydrodynamic model (Van Eysden and Sader, 2007 [6]) and a reduced order model (Heinisch et al., 2014 [16]) were employed to calculate the viscosity and mass density of the sample liquids in a viscosity range of 1–10.5mPas and a density range of 998–1154kgm−3.

이중 PLL 구조 주파수 합성기의 위상 잡음 개선

Abstract This paper proposes a high speed frequency synthesizer with dual phase-locked loop(PLL) structure to improve phase noise level and shape in a wideband receiver. To reduce phase noise and fractional spur, a output frequency of 1 st PLL used as reference frequency of 2 nd PLL is changed. The frequency synthesizer has been designed with 1 Hz frequency resolution using digital NCO in 6.5A8.5 GHz wide spectrum. The measured results of the fabricated frequency synthesizer show that the output power is about 3 dBm, the maximum lock-in time and phase noise are within 60 us and 95 dBc/Hz at 10 kHz offset, respectively.Key words: Frequency Synthesizer, Dual PLL, Phase Noise, Fractional Spur QRSTE%U(Agency for Defense Development)Manuscript received July 21, 2014 ; Revised September 5, 2014 ; Accepted September 12, 2014. (ID No. 20140721-11S)Corresponding Author: Jung-Hoon Kim(e-mail: jhkim1@add.re.kr) V. 서 론 WXY!Z [O ], Y!^_`, abcdefg9hi j 3klm, 9no#_ Npq mHr s*2tudvwN3klm-. Y!Z udv'( )* LO(Local Oscillator) 1wx23y0z{|}#-. '( )*)*R~€‚ #9ƒ„'( )*(DS: Direct Synthe-sis), „)*R~(PLL), ƒ„BCD)*R~(DDS: Direct Digital Synthesis) eG†‡ˆlm

A PVT Insensitive Vernier-Based Time-to-Digital Converter With Extended Input Range and High Accuracy

A monolithic Vernier-based time-to-digital converter (TDC) with 37.5 ps time resolution and theoretically unlimited input range has been integrated in TSMC 0.35-mum standard 2P4M CMOS technology. Since the proposed circuit utilizes a single-stage Vernier delay line (VDL) for both coarse and fine measurements, no other interpolation circuit is required. The operation frequencies of the single-stage Vernier delay line are stabilized against process, voltage and temperature (PVT) variations by dual phase-locked loops. The proposed TDC successfully eliminates the element mismatch, input range limitation, external bias adjustment and complicated calibration problems. The measured differential nonlinearity is plusmn0.2 LSB, and the measured integral nonlinearity is plusmn0.35 LSB. The power consumption is 150 mW at 100 k samples/s full conversion speed, and the chip size is as small as 0.222 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . All the packaged chips were tested to be fully functional over -40degC to 100degC ambient temperature range and 3.0 V to 3.9 V supply voltage range with extremely low resolution variations

High-Spectral Purity RF Beat Note Generated by a Two-Frequency Solid-State Laser in a Dual Thermooptic and Electrooptic Phase-Locked Loop

Ultralow noise stabilization of a two-frequency solid-state laser is experimentally demonstrated using a specially designed dual phase-locked loop. Thanks to an intracavity birefringent crystal providing both thermooptic and electrooptic frequency modulation properties, the laser delivers a beat frequency that is controlled by both pump power and voltage from 0 to 1000 MHz. When phase-locked against a radio-frequency synthesizer, the beat note has a 25-mHz full-width at half-maximum. The measured phase noise is -110 dBc/Hz at 10-kHz offset, and lower than -130 dBc/Hz at 1-MHz offset and above. Improvements and applications to local oscillators in microwave-photonic systems are discussed.

A dual phase-locked loop for vortex flow metering

A vortex-shedding flow meter produces an approximately sinusoidal signal whose average frequency is proportional to volumetric flow rate. The frequency of vortex shedding varies over a large range (up to 1:100), depending on the size of the flow meter. The conventional frequency estimator uses a zero-crossing algorithm (ZC), but this approach fails at low flows, where the signal-to-noise ratio is poor. An alternative is to use a phase-locked loop (PLL), but typical single PLL designs cannot cope with a wide frequency range at high noise levels. This paper describes a dual PLL structure that can be used to track the vortex shedding frequency over the flow meter’s full range of operation. This dual PLL provides improved accuracy and tracking ability compared with the conventional zero-crossing algorithm.

Validation of vortex flowmeters

A vortex-shedding flow meter produces an approximately sinewave signal whose average frequency is proportional to volumetric flow rate. The frequency of vortex shedding varies over a large range (up to 1:100), depending on the size of the flow meter. The conventional frequency-estimation method-a zero-crossing algorithm-fails at low flows, where the signal:noise ratio is poor. The paper describes a dual phase-locked loop structure that tracks the frequency over the flowmeter&apos;s full range with improved accuracy. The lock indicators associated with each PLL provide the SEVA metrics.

Wide-band π/2 phase shifter using a stepped sweeping dual phase-locked loop technique

A wide-band π/2 phase shifter based on stepped sweeping phase-locked loops (PLLs) is introduced and constructed. Results indicate that the system can work over a wide range of input frequencies limited only by the gain and saturation of the voltage-controlled oscillator (VCO) of the PLLs. For a noise-free signal, the phase error between the input and the π/2 phase-shifted output is 3° and it is constant regardless of the input frequency. The system can be modified to produce any phase shift from 0 to n with the same performance.

New dual digital phase‐locked loop

AbstractIn the phase‐locked loop (PLL), the following mehods are used to eliminate the steady‐state phase error produced by the input signal with frequency off‐set: (1) the perfect integrator is used as the loop filter, realizing the perfect second‐order PLL; (2) the dual phase‐locked loop (DuLL) is constructed by combining two first‐order PLL's, realizing a perfect second‐order PL, L. Method (1) has the problem of VCO drift, and method (2) has the problem that the choice of the loop constant (damping factor) is limited. Furthermore, both methods have the problem of unsatisfactory performance for the interfacing signal. This paper proposes a new DuLL which is constructed by adding a feedback circuit from the second PLL to the first PLL in the conventional DuLL. By theoretical analysis, it is shown that the new DuLL can remedy the problems in conventional circuits. Then the circuit is constructed by a digital signal processing technique. The pull‐in and interference characteristics are examined by computer simulation, indicating that the new DuLL has excellent characteristics.