이중 PLL 구조 주파수 합성기의 위상 잡음 개선

Abstract

Abstract This paper proposes a high speed frequency synthesizer with dual phase-locked loop(PLL) structure to improve phase noise level and shape in a wideband receiver. To reduce phase noise and fractional spur, a output frequency of 1 st PLL used as reference frequency of 2 nd PLL is changed. The frequency synthesizer has been designed with 1 Hz frequency resolution using digital NCO in 6.5A8.5 GHz wide spectrum. The measured results of the fabricated frequency synthesizer show that the output power is about 3 dBm, the maximum lock-in time and phase noise are within 60 us and 95 dBc/Hz at 10 kHz offset, respectively.Key words: Frequency Synthesizer, Dual PLL, Phase Noise, Fractional Spur QRSTE%U(Agency for Defense Development)Manuscript received July 21, 2014 ; Revised September 5, 2014 ; Accepted September 12, 2014. (ID No. 20140721-11S)Corresponding Author: Jung-Hoon Kim(e-mail: jhkim1@add.re.kr) V. 서 론 WXY!Z [O ], Y!^_`, abcdefg9hi j 3klm, 9no#_ Npq mHr s*2tudvwN3klm-. Y!Z udv'( )* LO(Local Oscillator) 1wx23y0z{|}#-. '( )*)*R~€‚ #9ƒ„'( )*(DS: Direct Synthe-sis), „)*R~(PLL), ƒ„BCD)*R~(DDS: Direct Digital Synthesis) eG†‡ˆlm