Dual Material Surrounding Gate Research Articles

Analytical Modeling of Surrounding Gate Junctionless MOSFET Using Finite Differentiation Method

In this paper, a novel two-dimensional analytical model for threshold voltage on Dual Material Surrounding Gate Junctionless MOSFET is proposed. The analytical study is aimed at decomposing the 2-D Poisson Equations into two 1-D equations. This decomposition enables modeling of Dual Material Gates into two individual single gates. For this prospect, the Finite Differentiation Method is applied. The decomposed individual 1-D Poisson models are combined by employing relevant boundary constraints. This, in turn, provides a normal and easy solution for equation related to complex 2-D Poisson. The proposed potential model facilitates expressions of threshold voltage and sub-threshold swing. Finally, the simulation results and the analytical results were compared with the simulations obtained from TCAD which showed significant compatibility. Thus, it is defended that the proposed model illustrates the guidance regarding the designing of Dual Material Surrounding Gate Junctionless MOSFETs.

Shallow Extension Engineered Dual Material Surrounding Gate (SEE-DM-SG) MOSFET for improved gate leakages, analysis of circuit and noise performance

The leakages in off state, particularly Gate Induced Drain Leakage (GIDL) has been addressed and reduced by proposing a Shallow Extension Engineered Dual Material Surrounding Gate (SEE-DM-SG) MOSFET. The shallow extensions create an insulating layer, which acts as a diffusion stopper and thereby suppresses the off state leakages. It is done by comparing the off-state performance of SEE-DM-SG MOSFET with Dual Metal Surrounding Gate (DM-SG) MOSFET and Surrounding Gate (SG) MOSFET. GIDL current is being reduced to an order of 10−12 A. Drain Induced Barrier Lowering (DIBL) has been curtailed to a greater extent in SEE-DM-SG MOSFET when compared with DM-SG MOSFET and SG MOSFET. GIDL has been extensively investigated for different drain voltages and temperatures; in order to study their impact on it. It was so found that GIDL was minimal for SEE-DM-SG MOSFET under different bias and temperature conditions. Arrhenius plot has also been plotted and deeply investigated as it instigates the GIDL activation energy (EA). It has been so found that SEE-DM-SG MOSFET poses higher EA and thereby suggests minimal BTBT (Band To Band Tunneling). So as to enhance the device applicability for low noise amplifier, the noise performance of SEE-DM-SG MOSFET has also been deeply investigated. Noise conductance (NC) and Noise Figure (NF) have been significantly curtailed in SEE-DM-SG MOSFET over DM-SG and SG MOSFET. A CMOS inverter has also been designed using SEE-DM-SG MOSFET and the output characteristics have also been compared for the aforesaid device architectures and higher Noise Margin has been observed in SEE-DM-SG MOSFET, making it more immune to noise.

Subthreshold Performance Analysis of Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel Field Effect Transistor for Ultra Low Power Applications

An improved subthreshold analytical model of Germanium source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel FET Ge(SRC)-DH-DD-TM-SG-TFET is proposed. The dielectric gate oxide structure is comprised of Silicon-dioxide and Hafnium oxide. The high-K dielectric materials overcomes the Short Channel Effects caused by ultrathin silicon devices. The subthreshold analysis is carried out by solving a 2-D Poisson’s equation using the parabolic approximation method. The electrical characteristics of Ge(SRC)-DH-DD-TM-SG-Tunnel FET are analyzed using a 3-D Sentaurus TCAD device simulator and compared with the silicon based single halo and triple material surrounding gate TFET structures. The proposed model shows a lower ambipolar current and a better ION/IOFF ratio of 106. Moreover, the influence of germanium/silicon in dual dielectric materials has reduced the tunneling barrier width and the ON current (10−4 A/μm) of the proposed device and improved at the level of CMOS transistors.

Performance Analysis of Noise in Dual Halo Dual Dielectric Triple Material Surrounding Gate MOSFET for RF Applications

Performance Analysis of Noise in Dual Halo Dual Dielectric Triple Material Surrounding Gate MOSFET for RF Applications

Analytical study of Dual Material Surrounding Gate MOSFET to suppress short-channel effects (SCEs)

In this paper, a 2D analytical model for the Dual Material Surrounding Gate MOSFET (DMSG) by solving the Poisson equation has been proposed and verified using ATLAS TCAD device simulator. Analytical modeling of parameters like threshold voltage, surface potential and Electric field distribution is developed using parabolic approximation method. A comparative study of the SCEs for DMSG and SMSG device structures of same dimensions has been carried out. Result reveals that DMSG MOSFET provides higher efficacy to prevent short-channel effects (SCEs) as compared to a conventional SMSG MOSFET due to the presence of the perceivable step in the surface potential profile which effectively screen the drain potential variation in the source side of the channel. A nice agreement between the results obtained from the model and the results obtained from numerical TCAD device simulator provides the validity and correctness of the developed model.

A New Two-Dimensional Analytical Threshold Voltage Model for Short-Channel Triple-Material Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors

A new analytical model for the surface potential and threshold voltage of triple-material surrounding-gate (TM-SGT) metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed to investigate short-channel effects (SCEs). The TM-SGT MOSFET forms a two-step potential in the channel and effectively reduces the SCEs and the variation of threshold voltage compared with those of dual-material surrounding-gate (DM-SGT) and triple-material double-gate (TM-DG) MOSFETs. TM-SGT MOSFETs thus have better performance than DM-SGT and TM-DG MOSFETs.

A New Two-Dimensional Analytical Threshold Voltage Model for Short-Channel Triple-Material Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors

A new analytical model for the surface potential and threshold voltage of triple-material surrounding-gate (TM-SGT) metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed to investigate short-channel effects (SCEs). The TM-SGT MOSFET forms a two-step potential in the channel and effectively reduces the SCEs and the variation of threshold voltage compared with those of dual-material surrounding-gate (DM-SGT) and triple-material double-gate (TM-DG) MOSFETs. TM-SGT MOSFETs thus have better performance than DM-SGT and TM-DG MOSFETs.

Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-κ gate dielectric

By solving Poisson's equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal—oxide semiconductor field-effect transistor (MOSFET) with a high-κ gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-κ dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.

2D Transconductance to Drain Current Ratio Modeling of Dual Material Surrounding Gate Nanoscale SOl MOSFETs

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

A new compact subthreshold behavior model for dual-material surrounding gate (DMSG) MOSFETs

On the basis of exact resultant solution of two-dimensional Poisson equation, a new compact subthreshold behavior model comprising two-dimensional potential, threshold voltage, subthreshold current and subthreshold swing for the dual-material surrounding gate (DMSG) MOSFETs is successfully developed. The model shows its validity by a good agreement with the simulated results from published device simulation software MEDICI. Besides offering the physical insight into device physics, the model provides the basic designing guidance for the DMSG MOSFETs.

Analytical Modeling and Simulation of Dual-Material Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Single-Halo Doping

We present a modified surrounding-gate metal–oxide–semiconductor field effect transistor (MOSFET), in which the gate consists of two metals with different work functions, and single-halo doping is added to the channel near the source end. The performance of the modified structure was studied by developing physics-based analytical models for the surface potential, electric field, and threshold voltage. It is shown that the novel MOSFET could significantly reduce threshold voltage roll-off and drain-induced barrier lowering, and simultaneously improve carrier transport efficiency by carefully configuring the halo doping and work functions of the dual-material gate. The results predicted using the models are compared with those obtained with the three-dimensional simulator Davinci to verify the accuracy of the proposed analytical models.

Dual-Material Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Asymmetric Halo

Asymmetrical halo and dual-material gate structure are used in the sub-100nm surrounding-gate metal–oxide–semiconductor field effect transistor (MOSFET) to improve the performance. Using three-region parabolic potential distribution and universal boundary condition, analytical surface potential and threshold voltage models of the novel MOSFET are developed based on the solution of Poisson's equation. The performance of the MOSFET is examined by the analytical models and the 3D numerical device simulator Davinci. It is shown that the novel MOSFET can suppress short channel effect and improve carrier transport efficiency. The derived analytical models agree well with Davinci.

An Analytical Modeling of Threshold Voltage and Subthreshold Swing on Dual Material Surrounding Gate Nanoscale MOSFETs for High Speed Wireless Communication

A new two dimensional (2-D) analytical model for the Threshold Voltage on dual material surrounding gate (DMSG) MOSFETs is presented in this paper. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expression for the threshold voltage and subthreshold swing is derived. It is seen that short channel effects (SCEs) in this structure is suppressed because of the perceivable step in the surface potential which screens the drain potential. We demonstrate that the proposed model exhibits significantly reduced SCEs, thus make it a more reliable device configuration for high speed wireless communication than the conventional single material surrounding gate (SMSG) MOSFETs.

A New Scaling Theory for the Effective Conducting Path Effect of Dual Material Surrounding Gate Nanoscale MOSFETs

In this Paper, we present a scaling theory for dual material surrounding gate (DMSGTs) MOSFETs, which gives a guidance for the device design and maintaining a precise subthreshold factor for given device parameters. By studying the subthreshold conducting phenomenon of DMSGTs, the effective conductive path effect (ECPE) is employed to acquire the natural length to guide the design. With ECPE, the minimum channel potential is used to monitor the subthreshold behavior. The effect of ECPE on scaling factor significantly improves the subthreshold swing compared to conventional scaling rule. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.