Dual Interlocked Storage Cell Research Articles

A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI

In this paper, we propose a low-power area-efficient redundant flip-flop for soft errors, called DICE-ACFF. Its structure is based on the reliable DICE (Dual Interlocked storage CEll) and the low-power ACFF (Adaptive-Coupling Flip-Flop). It achieves lower power at lower data-activity. We designed DICE-FF and DICE-ACFF using 65 nm conventional bulk and thin-BOX FD-SOI (Silicon on Thin-BOX, SOTB) processes. Its area is twice as large as the conventional DFF. As for power dissipation, DICE ACFF achieves lower power than the conventional DFF below 20% data activity. When data activity is 0%, its power is half of the DFF. As for soft error rates DICE ACFFs are 1.5x better than conventional DICE FFs based on circuit-level simulations to estimate critical charge. No SEU is observed on the DICE ACFF by α-particle and neutron irradiations on the bulk and SOTB chips. From neutron irradiation results, the soft error rate of the DFF of the SOTB chip is 1/15 compared with that of the bulk chip.

Heavy Ion Characterization of a Radiation Hardened Flip-Flop Optimized for Subthreshold Operation

A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suited for very-low power electronics that operate in subthreshold ( < Vt ≈ 500 mV). The proposed flip-flop along with a traditional (unprotected) flip-flop, a Sense-Amplifier-based Rad-hard Flip-Flop (RSAFF) and a Dual Interlocked storage Cell (DICE) flip-flop were all fabricated in MIT Lincoln Lab’s XLP 0.15 μm fully-depleted SOI CMOS technology—a process optimized for subthreshold operation. At the Cyclotron Institute at Texas A&M University, all four cells were subjected to heavy ion characterization in which the circuits were dynamically updated with alternating data and then checked for SEUs at both subthreshold (450 mV) and superthreshold (1.5 V) levels. The proposed flip-flop never failed, while the traditional and DICE designs did demonstrate faulty behavior. Simulations were conducted with the XLP process and the proposed flip-flop provided an improved energy delay product relative to the other non-faulty rad-hard flip-flop at subthreshold voltage operation. According to the XLP models operating in subthreshold at 250 mV, performance was improved by 31% and energy consumption was reduced by 27%.

Heavy Ion Characterization and Monte Carlo Simulation on 32 nm CMOS Bulk Technology

Heavy ion experimental test results carried out on static random-access memories (SRAMs) manufactured in bulk complementary metal-oxide semiconductor (CMOS) 32 nm are compared to Monte Carlo simulations. Additional simulation capabilities allow for insight in heavy ion cross-section variations as a function of temperature, power supply voltage, and process corners. Monte Carlo simulations of a radiation-hardened-by-design flip-flop based on a dual-interlocked storage cell latch have been performed and show similar sensitivities for 65 nm and 32 nm technologies. Finally, for the first time, the heavy-ion cross-section of the 20 nm bulk CMOS SRAMs is anticipated by simulation by using the latest available technology data.

Memory-cell layout as a factor in the single-event-upset susceptibility of submicron dice CMOS SRAM

Computer simulations with the Spectre circuit simulator from Cadence Design Systems and a proton-accelerator experiment are conducted to investigate the relationship of single-event-upset (SEU) susceptibility to memory-cell layout in the context of a 0.18-μm CMOS SRAM using the dual interlocked storage cell (DICE) technology with differing separations of the pair transistors designed to store a 0 or 1, namely, 0.9 and 2.5 μm, respectively. The simulated values of critical charge for an upset are found to be greater by a factor of 10 for the wider separation. With 1-GeV proton irradiation, using the wider separation of pair transistors is found to reduce the SEU count by a factor of 5.5–15 (depending on the supply voltage). In the experiment, lowering the supply voltage of the memory bank from 1.8 to 0.7 V is found to increase on average the SEU cross section by a factor of 3. Close agreement is observed between the simulated and measured results.

Monte-Carlo Based Charge Sharing Investigations on a Bulk 65 nm RHBD Flip-Flop

Charge sharing in a dual-interlocked storage cell (DICE) Flip-Flop (FF) manufactured in 65 nm CMOS Bulk is analyzed using a new proprietary Monte-Carlo tool suite named TIARA (Tool suIte for rAdiation Reliability Assessment). Monte-Carlo simulations show the simultaneous charge collection by transistors in the same well is 5 X more important than charge sharing in different wells. Additionally, TIARA simulations are used to identify layout weaknesses. Subsequent layout modifications have increased the threshold LET by 50%.

Features of design of submicron CMOS of Static RAMs with an increased failure resistance to the effect of high-energy particles

The results of the comparative investigation of CMOS memory cells with a 0.18-μm design rule showed that the best parameters both in terms of their failure resistance to the effects of the influence of separate high-energy particles and in terms of sizes and speed are inherent to the DICE (Dual Interlocked Storage Cell) memory cells. According to the results of the design of single-ported and dual-ported 0.18-μm CMOS RAM units, based on DICE memory cells and with the use of constructive measures of protection from the thyristor effects, specifically, contacts to the substrate and n-pockets and guard rings, the coefficients of consumption of the crystal area for the banks of memory cells, units of control logic, interconnections, and RAM supply ring are substantiated. The increase in the RAM area is not larger than by a factor of 1.7–2.7, with the conservation of speed and increase in supplied consumption by a factor of 1.4–2.0 for RAM with a capacity of up to 128 Kbit; for a RAM capacity of 1 Mbit, the coefficient of the increase in area is 3.1, with the provision of the maximum failure resistance for the static RAM by bulk CMOS technology with a 0.18-μm design rule.

Operability analysis of submicron CMOS-based VLSI RAMs operated under extreme thermal conditions

Variations in the characteristics of the memory cells of submicron CMOS RAMs caused by changes in temperature were simulated and experimentally investigated in a wide temperature range of minus 50°C to +150°C. It was found that submicron VLSI circuits fabricated on the basis of the 0.35-μm bulk-CMOS technology with epitaxial layers and of the industrial 0.18-μm bulk-CMOS technology are, in the large, characterized by high maximum permissible temperatures. The simulation results were confirmed by the tests of submicron 0.35- and 0.18-μm CMOS RAMs based, respectively, on 6-transistor and 12-transistor memory cells with heavy-ion tolerant (HIT) and dual interlocked storage-cell (DICE) structures. The results of the investigation allow one to make a reasoned selection of memory cells to be used in practical embodiments of VLSI static RAMs intended to operate under extreme conditions

Schemes for eliminating transient-width clock overhead from SET-tolerant memory-based systems

In the presence of radiation, particle strikes can cause temporary signal errors in ICs. Particle strikes that directly affect memory are known as single event upsets (SEUs), while strikes that affect combinational logic and spread to memory are called single event transients (SETs). In this paper, we propose two novel approaches to hardening integrated circuits against SEUs and SETs. The proposed approaches are fully-differential dual-interlocked storage cell (DICE) and triple path DICE (TPDICE). The fully-differential DICE and TPDICE approaches are compared against two existing approaches, which are triple modular redundancy (TMR) and basic SET-tolerant DICE. All approaches except for the basic SET-tolerant DICE scheme share a common theme, which is the ability to bypass SEUs and SETs. This is critical for performance, as it allows the system to proceed with subsequent operations while a cell is recovering from the effects of a particle strike. SET pulse widths can be substantial (up to 2 ns), and so high-performance systems cannot afford to pause operations while these pulses are present. The minimum clock periods obtained for the basic SET-tolerant approach were 515 ps with no SET, and 1310 ps with a 500 ps SET (in 0.18 /spl mu/m CMOS). In contrast, the clock periods for the bypass-capable approaches with no SET/500 ps SET were 628/749 ps for TMR, 348/480 ps for fully-differential DICE, and 434/552 ps for TPDICE. Among the approaches that bypass transient pulses, TPDICE is the most balanced. TMR suffers from overhead due to its need for external voting circuitry. In addition to this, fully-differential DICE cannot be used with combinational logic, while TPDICE can.