Features of design of submicron CMOS of Static RAMs with an increased failure resistance to the effect of high-energy particles

Abstract

The results of the comparative investigation of CMOS memory cells with a 0.18-μm design rule showed that the best parameters both in terms of their failure resistance to the effects of the influence of separate high-energy particles and in terms of sizes and speed are inherent to the DICE (Dual Interlocked Storage Cell) memory cells. According to the results of the design of single-ported and dual-ported 0.18-μm CMOS RAM units, based on DICE memory cells and with the use of constructive measures of protection from the thyristor effects, specifically, contacts to the substrate and n-pockets and guard rings, the coefficients of consumption of the crystal area for the banks of memory cells, units of control logic, interconnections, and RAM supply ring are substantiated. The increase in the RAM area is not larger than by a factor of 1.7–2.7, with the conservation of speed and increase in supplied consumption by a factor of 1.4–2.0 for RAM with a capacity of up to 128 Kbit; for a RAM capacity of 1 Mbit, the coefficient of the increase in area is 3.1, with the provision of the maximum failure resistance for the static RAM by bulk CMOS technology with a 0.18-μm design rule.