Abstract
Heavy ion experimental test results carried out on static random-access memories (SRAMs) manufactured in bulk complementary metal-oxide semiconductor (CMOS) 32 nm are compared to Monte Carlo simulations. Additional simulation capabilities allow for insight in heavy ion cross-section variations as a function of temperature, power supply voltage, and process corners. Monte Carlo simulations of a radiation-hardened-by-design flip-flop based on a dual-interlocked storage cell latch have been performed and show similar sensitivities for 65 nm and 32 nm technologies. Finally, for the first time, the heavy-ion cross-section of the 20 nm bulk CMOS SRAMs is anticipated by simulation by using the latest available technology data.
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