Comparative Evaluation of different 3T DRAM Cells at 45nm Technology

Abstract

This study analyses and compares the performance of 3T bulk CMOS Dynamic Random Access (DRAM) cell, 3T FinFET (Fin Field Effect Transistor) DRAM cell and 3T FinFET based Capacitor-less DRAM cell designs. The designs were done at 45nm technology. FinFET is a good candidate for replacing bulk CMOS (Complementary Metal-Oxide Semiconductor) for future nanometer scale technology. The capacitor-less DRAM utilizes a gated diode as reservoir element as opposed to capacitor, this led to reduction in leakages and access time. A gated diode is a two terminal MOS in which charge is stored when gate to source voltage is greater than the threshold voltage; otherwise a negligible charge is stored. Memory design is one of the interesting subjects in semiconductor technology. Many modern processors use DRAM for on chip data and program memory. DRAM has dominated solid state memories used for primary storage in most advanced processors as compared to SRAM (Static Random Access Memory), because it occupies less area per cell. Off-state leakage is the major drawback of DRAM, so improving this leakage power will be critical to the system power dissipation. The three cells were designed and their average power, leakage parameters and noise were simulated on Cadence Virtuoso tool and the results were analyzed. We investigate that the use of FinFET Technology improves the performance of the DRAM as compared to bulk CMOS and also compare it to the DRAM with gated-diode. In this work it has shown that the 3T FinFET with gated-diode as the capacitor has better performance in terms of leakage parameters.