Dual-gate Device Research Articles

Tuning Exciton Emission via Ferroelectric Polarization at a Heterogeneous Interface between a Monolayer Transition Metal Dichalcogenide and a Perovskite Oxide Membrane.

We demonstrate the integration of a thin BaTiO3 (BTO) membrane with monolayer MoSe2 in a dual-gate device that enables in situ manipulation of the BTO ferroelectric polarization with a voltage pulse. While two-dimensional (2D) transition metal dichalcogenides (TMDs) offer remarkable adaptability, their hybrid integration with other families of functional materials beyond the realm of 2D materials has been challenging. Released functional oxide membranes offer a solution for 2D/3D integration via stacking. 2D TMD excitons can serve as a local probe of the ferroelectric polarization in BTO at a heterogeneous interface. Using photoluminescence (PL) of MoSe2 excitons to optically read out the doping level, we find that the relative population of charge carriers in MoSe2 depends sensitively on the ferroelectric polarization. This finding points to a promising avenue for future-generation versatile sensing devices with high sensitivity, fast readout, and diverse applicability for advanced signal processing.

Three-dimensional integrated metal-oxide transistors

AbstractThe monolithic three-dimensional vertical integration of thin-film transistor (TFT) technologies could be used to create high-density, energy-efficient and low-cost integrated circuits. However, the development of scalable processes for integrating three-dimensional TFT devices is challenging. Here, we report the monolithic three-dimensional integration of indium oxide (In2O3) TFTs on a silicon/silicon dioxide (Si/SiO2) substrate at room temperature. We use an approach that is compatible with complementary metal–oxide–semiconductor (CMOS) processes to stack ten n-channel In2O3 TFTs. Different architectures—including bottom-, top- and dual-gate TFTs—can be fabricated at different layers in the stack. Our dual-gate devices exhibit enhanced electrical performance with a maximum field-effect mobility of 15 cm2 V−1 s−1, a subthreshold swing of 0.4 V dec−1 and a current on/off ratio of 108. By monolithically integrating dual-gate In2O3 TFTs at different locations in the stack, we created unipolar invertor circuits with a signal gain of around 50 and wide noise margins. The dual-gate devices also allow fine-tuning of the invertors to achieve symmetric voltage-transfer characteristics and optimal noise margins.

P‐24: Ultra‐low power consumption notebook LCD with high on‐state current metal oxide device

Dual gate device with mobility of 20cm2/Vs has been applied to improve power consumption of oxide products, the devices show high on‐state current of more than 45uA, good uniformity of ΔVth 1.03V, PBTS of 2.18V. The optimized pixel design of 14inch WQXGA achieves high aperture ratio of 74% and transmittance of over 9.5%. This 120Hz demo with brightness of 150nit can significantly reduce power consumption by 65%, from 2.1W to 1.27W.

Field-Induced Hybridization of Moiré Excitons in MoSe_{2}/WS_{2} Heterobilayers.

We study experimentally and theoretically the hybridization among intralayer and interlayer moiré excitons in a MoSe_{2}/WS_{2} heterostructure with antiparallel alignment. Using a dual-gate device and cryogenic white light reflectance and narrow-band laser modulation spectroscopy, we subject the moiré excitons in the MoSe_{2}/WS_{2} heterostack to a perpendicular electric field, monitor the field-induced dispersion and hybridization of intralayer and interlayer moiré exciton states, and induce a crossover from type I to type II band alignment. Moreover, we employ perpendicular magnetic fields to map out the dependence of the corresponding exciton Landé g factors on the electric field. Finally, we develop an effective theoretical model combining resonant and nonresonant contributions to moiré potentials to explain the observed phenomenology, and highlight the relevance of interlayer coupling for structures with close energetic band alignment as in MoSe_{2}/WS_{2}.

High-speed, low-voltage, small-pitch and robust OTFT-based integrated gate driver for active-matrix displays

We design and fabricate a high-speed, low-voltage, small-pitch, and robust integrated gate driver with organic thin-film transistors (OTFTs). The dual-gate OTFT devices have a field effect mobility of 0.78 cm2/Vs, and on/off current ratio above 108. A single stage of the gate driver consists of ten TFTs and two capacitors, with small pitch of 244 μm. The fabricated circuit has a minimum pulse width of 5μs, which is compatible with full-high definition (FHD, 1920 × 1080) active-matrix displays with 60Hz frame rate. It can work at input swing of as low as 10V, with VGH2, VGH1, and VGL of 5V, 0V, and −10V respectively. With the threshold voltage shift under positive and negative bias stress, the gate driver shows output signals without significant degradation and demonstrates its high reliability through simulation.

Layer-dependent exciton polarizability and the brightening of dark excitons in few-layer black phosphorus

The evolution of excitons from 2D to 3D is of great importance in photo-physics, yet the layer-dependent exciton polarizability hasn’t been investigated in 2D semiconductors. Here, we determine the exciton polarizabilities for 3- to 11-layer black phosphorus—a direct bandgap semiconductor regardless of the thickness—through frequency-resolved photocurrent measurements on dual-gate devices and unveil the carrier screening effect in relatively thicker samples. By taking advantage of the broadband photocurrent spectra, we are also able to reveal the exciton response for higher-index subbands under the gate electrical field. Surprisingly, dark excitons are brightened with intensity even stronger than the allowed transitions above certain electrical field. Our study not only sheds light on the exciton evolution with sample thickness, but also paves a way for optoelectronic applications of few-layer BP in modulators, tunable photodetectors, emitters and lasers.

On the double channel engineering of dual gate AlGaN/GaN HEMTs for heavy ion sensing applications

This work investigates the influence of Single Event Transient (SET) effect on Double Channel Dual Gate (DC-DG) AlGaN/GaN HEMT using TCAD simulations. Both Single Channel (SC) and Double Channel HEMT have been calibrated with reported experimental results and further extended by introducing a second gate in the structures to analyze its sensitivity towards heavy ion strike. The effective gate length has been optimized in such a way that the saturation currents and threshold voltage of dual gate devices is similar to that of the single gate devices. The DC-DG HEMT improves the heavy ion sensitivity, thus making it a more viable device for sensing application (mainly radiation). Different biases and gate materials have been used to observe the influence of SET on the DC-DG AlGaN/GaN HEMT. Further, the impact of the graded AlGaN barrier on the device current as well as on the sensitivity of the DC-DG HEMT towards SET is studied. To ascertain the performance of DC-DG HEMT for dosimeter applications, its sensitivity toward heavy ion impact in switched mode is monitored. Investigation reveals that the device current returns to its original order of magnitude after every ion impact, and therefore can be effectively used as a dosimeter.

Cascaded Logic Gates Based on High-Performance Ambipolar Dual-Gate WSe2 Thin Film Transistors.

Ambipolar dual-gate transistors based on low-dimensional materials, such as graphene, carbon nanotubes, black phosphorus, and certain transition metal dichalcogenides (TMDs), enable reconfigurable logic circuits with a suppressed off-state current. These circuits achieve the same logical output as complementary metal-oxide semiconductor (CMOS) with fewer transistors and offer greater flexibility in design. The primary challenge lies in the cascadability and power consumption of these logic gates with static CMOS-like connections. In this article, high-performance ambipolar dual-gate transistors based on tungsten diselenide (WSe2) are fabricated. A high on-off ratio of 108 and 106, a low off-state current of 100 to 300 fA, a negligible hysteresis, and an ideal subthreshold swing of 62 and 63 mV/dec are measured in the p- and n-type transport, respectively. We demonstrate cascadable and cascaded logic gates using ambipolar TMD transistors with minimal static power consumption, including inverters, XOR, NAND, NOR, and buffers made by cascaded inverters. A thorough study of both the control gate and the polarity gate behavior is conducted. The noise margin of the logic gates is measured and analyzed. The large noise margin enables the implementation of VT-drop circuits, a type of logic with reduced transistor number and simplified circuit design. Finally, the speed performance of the VT-drop and other circuits built by dual-gate devices is qualitatively analyzed. This work makes advancements in the field of ambipolar dual-gate TMD transistors, showing their potential for low-power, high-speed, and more flexible logic circuits.

Field plated, gate work function engineered AlGaN channel HEMTs with improved DC, RF and power performance

This paper presents the study of the impact of gate work function engineering on the performance of AlGaN channel high electron mobility transistor. The proposed devices with dual material and triple material gate structures result in improved electrical characteristics. The devices exhibit a peak transconductance of 11.86 mS, 11.80 mS respectively for triple and dual material gate structures. A comparative analysis on the performance of the proposed device structures with that of a conventional AlGaN channel HEMT is presented. The devices are able to offer superior RF performance compared to the conventional device with fT values of 0.89 GHz, 0.889 GHz for triple material and dual material gate devices respectively. By incorporating gate field plates, field crowding at the gate edge can be reduced further. The field plated structure can cater to better high voltage operation with a slight penalty on the high frequency performance.

A dual-gate and Γ-type field plate GaN base E-HEMT with high breakdown voltage on simulation investigation

This paper proposes to insert a buried P-type gate (BPT gate) under the channel layer of the recessed MIS-high electron mobility transistor (HEMT) to form a dual-gate HEMT. And through simulation calculation, the device performance is calculated and the working mechanism of the BPT gate is explained in detail. Compared with a conventional AlGaN/AlN/GaN HEMT and a gate-recessed MIS-HEMT, the dual-gate HEMT has a higher breakdown voltage (1126 V) and a larger threshold voltage (1.5 V). The results show that inserting a BPT gate in a gate-recessed MIS-HEMT can increase the threshold voltage and improve the breakdown characteristics. Through the optimization of the device structure, it is found that the combination of the MIS-gate and the Γ-type field plate based on the dual-gate device can obtain a higher breakdown voltage. Its breakdown voltage can reach 3041 V, and the figure of merit is as high as 3.56 GW cm−2. This reveals that the combination of dual-gate and Γ-type field plate has great potential in the manufacture of enhancement-mode and high-voltage power transistors.

Simulation of FDSOI-ISFET with Tunable Sensitivity by Temperature and Dual-Gate Structure

This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.

Intrinsic coupling between spatially-separated surface Fermi-arcs in Weyl orbit quantum Hall states

Topological semimetals hosting bulk Weyl points and surface Fermi-arc states are expected to realize unconventional Weyl orbits, which interconnect two surface Fermi-arc states on opposite sample surfaces under magnetic fields. While the presence of Weyl orbits has been proposed to play a vital role in recent observations of the quantum Hall effect even in three-dimensional topological semimetals, actual spatial distribution of the quantized surface transport has been experimentally elusive. Here, we demonstrate intrinsic coupling between two spatially-separated surface states in the Weyl orbits by measuring a dual-gate device of a Dirac semimetal film. Independent scans of top- and back-gate voltages reveal concomitant modulation of doubly-degenerate quantum Hall states, which is not possible in conventional surface orbits as in topological insulators. Our results evidencing the unique spatial distribution of Weyl orbits provide new opportunities for controlling the novel quantized transport by various means such as external fields and interface engineering.

Strong and tunable spin\u2013orbit interaction in a single crystalline InSb nanosheet

A dual-gate InSb nanosheet field-effect device is realized and is used to investigate the physical origin and the controllability of the spin–orbit interaction in a narrow bandgap semiconductor InSb nanosheet. We demonstrate that by applying a voltage over the dual gate, efficiently tuning of the spin–orbit interaction in the InSb nanosheet can be achieved. We also find the presence of an intrinsic spin–orbit interaction in the InSb nanosheet at zero dual-gate voltage and identify its physical origin as a build-in asymmetry in the device layer structure. Having a strong and controllable spin–orbit interaction in an InSb nanosheet could simplify the design and realization of spintronic deceives, spin-based quantum devices, and topological quantum devices.

IGZO-TFT-PDK: Thin-Film Flexible Electronics Design Kit, Standard Cell and Design Methodology

With the increasing demand for transparent/flexible displays, healthcare sensors, and robotics, there is a need to advance the development of thin-film transistors (TFTs) manufacturing and large-scale circuits. This paper has proposed an IGZO-TFT-PDK to aid the educators and research community to explore the circuit design space of dual-gate IGZO-TFT devices. To solve the tensile force-induced current variation problem in IGZO-TFT devices, an omni-directional device and its layout template with a compensation methodology that mitigates its variation are proposed. A layout template is also proposed to speed up the design development flow of both analog and digital IGZO-TFT circuits. Based on the proposed layout template, a tensile force-insensitive standard cell library is proposed. We have implemented a 32-bit carry select adder to validate the usability of the standard cell library.

Strategic Review on Different Materials for FinFET Structure Performance Optimization

In this paper, the strategic review of different materials that are used in FinFET structure is studied. This is achieved by using carefully designed source/drain spacers and doped extensions to mitigate the off-current, typically high in narrow band-gap materials, as part of a CMOS compatible replacement-metal gate process flow. FinFETs are promising substitutes for bulk complementary metal oxide semiconductor. FinFETs are dual-gate devices and Good electrostatic characteristics which are obtained in a wide range of device dimensions. The simulations provide further insights into device functionality and about the dominant off-state leakage mechanisms. The GaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. In this various types of materials are used and studied they are FinFET based Dual KK-structure, InGaAs-on-Insulator FinFET, Double Gate based n-FinFET using Hafnium oxide, SOI-FinFETs, MosFET (Multi gate), Deeply Scaled CMOS, FinFET, Selective Epitaxial Si Growth in FinFET and Atomic Layer Deposition (ALD) in FinFET. Furthermore, we demonstrate a controlled GaAs digital etching process to create doped extensions below the source-drain spacer regions.

Investigation of Dual Metal Gate Schottky Barrier MOSFET for Suppression of Ambipolar Current

In this paper, a simulation study to suppress the ambipolar current of the Schottky Barrier (SB) MOSFET is presented. In this work, a dual metal gate device structure is used. The gate of the device is composed of two different metals. The metal used at the source side gate is used region has higher work function, while the metal used at the drain side gate region has lower work function. To perform this study, the work function of the gate metal used at the source end is kept fixed. On the other hand, to choose the appropriate metal for gate at the drain end, different work function metal has been employed. Therefore, without affecting the on-state current of the device, ambipolar current has been suppressed. In addition, the performance of the proposed device has been compared with the conventional SB MOSFET. Simulation results show that the proposed device exhibits more than two-decade reduction in ambipolar current than the conventional double gate SB MOSFET.

Electrothermal analysis of novel N-P-P FinFET with electrically doped drain: a dual material gate device for reliable nanoscale applications

In this paper, we offer a new structure of N+-P-P Fin Field Effect Transistor (FinFET) with a dual material gate in which the drain side P–N junction has been physically removed. The P-type drain consists of two parts, depletion region (DR) and electrically doped (ED) area, where the ED region is surrounded by an extra gate with optimized length and appropriate work function made of barium (B-gate). The ED region located under the B-gate is converted to N+ drain using the charged plasma (CP) concept to design the CP-FinFET. Improved ability to control the hot carrier effect by amending the critical electric field is the main idea of this work. The p-type depletion region (DR) created between the silicon active layer and electrically doped drain eliminates the gate-drain overlap and reduces the charge sharing and short channel effects (SCE). The modified electric field in the DR region offers advantages including improved hot-electron reliability and high-performance devices. Therefore, in the CP-FinFET the degradation mechanism improves due to the hot carrier effect (HCE) reduction. Indeed, the improvement in device performance is investigated using three-dimensional Atlas simulator with concentrating on the gate current, off-state current, reliability, electron temperature and gate induced drain leakage (GIDL). The comparison results demonstrate the superiority of the proposed structure as a high-efficiency device to design reliable Complementary metal–oxide–semiconductor circuits in nanoscale.

Characteristics of Dual‐Gate Graphene Thermoelectric Devices Based on Voltage Regulation

A dual-gate graphene thermoelectric device structure is proposed. Under the control of back-gate and top-gate voltage, the type and degree of carrier transport in graphene channels can be changed, where the absorption and release of heat are controlled at the contact between graphene and metal electrodes. More details can be found in article number 1901466 by Xiumin Gao and co-workers.

Transparent Flexible High Mobility TFTs Based on ZnON Semiconductor With Dual Gate Structure

High mobility thin film transistors (TFTs) based on zinc oxynitride (ZnON) semiconductor were fabricated onto polyethylene-2.6-naphthalate (PEN) substrates. The application of a dual gate structure enhanced the field-effect mobility from 65.8 to 147 cm2/ $\text{V}\cdot \text{s}$ , which is generally attributed to the bulk accumulation effect. Dual gate driving also results in improved device stability with respect to bias and illumination stress. This is most likely due to the fact that the bulk channel confines the charge carriers away from the semiconductor-dielectric interfaces, where charge trapping is anticipated. The electrical performance of dual gate devices did not change significantly after 5,000 bending cycles, while the single gate transistors exhibited clear degradation.

Noise test method for dual-gate MOSFET device

In recent years, with the development of mesoscopic physics and nanoelectronics, the research on noise and testing technology of electronic components has been developed. It is well known that noise can characterize the transmission characteristics of carriers in nanoscale electronic components. With the continuous shrinking of the device size, the carrier transport of nanoscale MOSFET devices has been gradually transformed from the traditional drift-diffusion to become the quasi-ballistic or ballistic transport, and its current noise contains granular and thermal noise. The paper by Jeon et al. [The first observation of shot noise characteristics in 10-nm scale MOSFETs, in Proc. 2009 Symp. VLSI Technology (IEEE, Honolulu, 2009), pp. 48–49] presents the variation relation of 20 nm MOSFET current noise with source–drain current and voltage, and its current noise characteristic is between thermal noise and shot noise, so 20 nm MOSFET current noise is shot noise and thermal noise. The paper by Navid et al. [J. Appl. Phys. 101 (2007) 124501] shows through simulation that the 60 nm MOSFET current noise is suppressed shot noise and thermal noise. At present, the current noise has seriously affected the basic performance of the device, thus the circuit cannot work normally. Therefore, it is necessary to study the generation mechanism and characteristics of current noise in electronic components so as to suppress device noise, which can not only realize the reduction of device noise, but also play a positive role in the work-efficiency, life-span and reliability of electronic components.