Abstract
This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.
Highlights
Since the ion-sensitive field-effect transistor (ISFET) was firstly proposed by P
Due to the existence of the Nernst limit of 59.6 mV/pH at room temperature [8], determining how to improve the sensitivity of ISFETs has been a major concern for researchers
Many structures have been utilized to increase the sensitivity of ISFETs, which are compatible with the CMOS process [14]
Summary
Since the ISFET was firstly proposed by P. Many methods have been explored to improve the sensitivity of ISFETs. Many methods have been explored to improve the sensitivity of ISFETs These methods can be categorized into two types: changing the material and changing the structure. The AlGaN/GaN heterojunction [9] and Si3 N4 [10] are used to replace silicon substrate, while Si3 N4 [10], Al2 O3 [11], Ta2 O5 [12,13] and many other metal oxides are used to replace SiO2 as the sensitive layer of ISFETs. At the same time, many structures have been utilized to increase the sensitivity of ISFETs, which are compatible with the CMOS process [14]. Examples include using an ultrathin body and buried oxide (UTBB) FDSOI ISFET, in which the sensing area and the control gate are integrated into the backend of the line (BEOL) [8,15,16,17], or using a planar dual-gate high-electron-mobility transistor (HEMT) as an ISFET [5]
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