Dual-direction SCR Research Articles

A Novel Dual-Direction SCR Embedded With Segmental and Cross-Bridge Topology for High-Voltage ESD Protection

A novel dual-direction silicon-controlled rectifier (DDSCR) embedded with segmental and cross-bridge topology, which is named DDSCRESCT, is proposed and optimized for electrostatic discharge (ESD) protection. By segmenting N <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{+}$</tex-math> </inline-formula> bridges and inserting a P <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{+}$</tex-math> </inline-formula> bridge in DDSCR, the trigger voltage of the DDSCRESCT decreases to 10.3 V, which is attributed to the multiple avalanche breakdown effects. By embedding a floating N-type well in DDSCR, the holding voltage of the DDSCRESCT increases to 7.8 V, due to the low current gain of the parasitic bipolar junction transistors. Compared to DDSCR, the leakage current of the DDSCRESCT decreases about one order of magnitude and achieves a large failure current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{I}_{\textit{t}\text{2}}$</tex-math> </inline-formula> ) of 3.6 A, resulting from the segmental and cross-bridge topology design. By optimizing the length of the N <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{+}$</tex-math> </inline-formula> segmental topology and the width of the P <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{+}$</tex-math> </inline-formula> implanted bridge across the P-type well, the DDSCRESCT exhibits a good clamping ability and a decreased turn-on resistance of 2.1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $</tex-math> </inline-formula> , resulting in a further <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim$</tex-math> </inline-formula> 16.2% increase of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{I}_{\textit{t}\text{2}}$</tex-math> </inline-formula> . The human body model (HBM) test of the DDSCRESCT with a finger width of 100 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> m can reach 4 kV due to the optimized segmental and cross-bridge topology design, which also offers great potential in providing high-voltage ESD protection.

A Novel Gate-Controlled Dual Direction SCR With Enhanced Failure Current for On-Chip ESD Protection of Industry-Level Controller Area Network Bus

The working environment of the industry-level high-voltage communication bus is harsh. Strong electrostatic interference has become one of the key factors affecting the stability of the core module. However, the traditional silicon-controlled rectifier (SCR) is difficult to meet the electrostatic discharge (ESD) design requirements for high-voltage applications. Therefore, this article proposes a novel enhanced gate-controlled dual-direction SCR (EGC-DDSCR) with a high failure current, which can effectively ensure the ESD reliability of the controller area network (CAN) bus. By comparing the ESD performance of EGC-DDSCR, traditional gate-controlled DDSCR (GC-DDSCR), and double-GC-DDSCR (DGC-DDSCR), the physical behavior of the gate control mechanism is explored. Three types of SCR are designed based on a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> BCD process. According to the physical principles of devices, 2-D electrical simulation and transmission line pulse (TLP) test results predict and verify the ESD parameters of the SCRs. The results show that EGC-DDSCR ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.64~\Omega$ </tex-math></inline-formula> ) has a smaller ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{\mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> ) and higher robustness than GC-DDSCR ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.98~\Omega$ </tex-math></inline-formula> ) and DGC-DDSCR ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.90~\Omega$ </tex-math></inline-formula> ). In addition, the trigger voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{t1}$ </tex-math></inline-formula> :42.7 V), holding voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{h}$ </tex-math></inline-formula> :31.0 V), and failure current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{t2}$ </tex-math></inline-formula> :16.7 A) of the device fully meet the ESD window of the target chip. EGC-DDSCR can be stably applied to CANL and CANH interfaces for on- chip bidirectional ESD protection.

Analyzing the impact of guard-ring on different dual-direction SCR by device simulation and TLP measurement

In this paper, the impact of the traditional interdigital DDSCR structure (TI-DDSCR) and the embedded DDSCR (EM-DDSCR) structure with and without P+ guard-ring is analyzed under the 0.5-μm complementary and double-diffused MOSFET (CDMOS) technology. In order to verify and predict the characteristics of those electrostatic discharge (ESD) protection devices, a transmission line pulse (TLP) testing system and device simulation platform have been used in this work. The test results show that the introduction of P + guard ring will increase the device forward trigger voltage (Vt1) by about 3 V and forward holding voltage (Vh) by 4-6 V, but has little effect on the forward failure current (It2). The reverse Vh is reduced by 4–6 V, while the reverse It2 depends on the layout geometry. Due to the different layout geometry, on the TI-DDSCR structure with P+ guard ring, their reverse It2 is reduced from 13.07A to 8.05A. On the contrary, on the EM-DDSCR with P+ guard ring, their reverse It2 increased from 6.55A to 10.10A.

Design and analysis of a multi-finger dual-direction SCR discharging electro-static current in a gradual transition manner

In order to seek an electro-static discharge with higher failure current per unit area and latch-up immunity, a novel multi-finger dual-direction silicon controlled rectifier (DDSCR) using the 0.5 μm complementary and double-diffusion metal-oxide-semiconductor technology was proposed. The working principle of the device is analyzed by using equivalent circuit and technology computer aided design simulation. From the test result of the transmission line pulse testing system we can see that the holding voltages for the traditional dual-direction silicon controlled rectifiers with a single-finger and two-fingers are 11.34 V and 7.63 V, respectively, which is decreased as the number of fingers increases. The holding voltage of the proposed device is 12.2 V, which is higher than that of the traditional 2-finger DDSCR and suitable for communication interface high voltage electrostatic discharge (ESD) protection. Furthermore, the influence of some dimensions, fingers and total finger width on the device is discussed. The proposed device not only solves the problem of decreasing the holding voltage caused by increasing the number of fingers, but also has a slight effect on the failure current. The root cause for such holding voltage trend is their different working mechanisms. The proposed device is turning on one finger by another instead of simultaneously turning on in the multi-finger traditional devices. Therefore, the proposed ESD device owns a holding voltage similar to that of the 1-finger device.

A Radiation-Hardened Dual-Direction SCR Based on LDMOS for ESD Protection in the Extreme Radiation Environment

To mitigate the total ionizing dose (TID) effects of the dual-direction silicon-controlled rectifier, based on laterally diffused metal–oxide–semiconductor (LDMOS-DDSCR), a common-centroid layout arrangement with multiple octagonal units is proposed and fabricated in an 18-V Bipolar-CMOS-DMOS process. The symmetrical characteristics of the bidirectional electrostatic discharge (ESD) protection are verified by transmission line pulse tests. Gamma-ray irradiation experiments demonstrate that the proposed device is tolerant of TID effects up to 100 krad(Si), whereas the traditional finger-type LDMOS-DDSCR loses its function at 50 krad(Si). Finally, the ESD performance is also characterized at high temperatures which confirms that the proposed device is an excellent candidate for space applications.

The impact of radiation and temperature effects on dual-direction SCR devices for on-chip ESD protections

The reliability issues of integrated circuits are attracting more attention, especially in extreme environments like radiation and elevated temperature conditions. The impact of ionizing radiation and temperature effects on the electrostatic discharge (ESD) protection devices should not be negligible. In this paper, A low-voltage dual-direction silicon controlled rectifier (DDSCR) and a high-voltage DDSCR based on laterally diffused metal oxide semiconductor are chosen and fabricated in a 5 V/18 V Bipolar-CMOS-DMOS process. To study the combined effects of ESD and total-ionizing dose, transmission line pulse (TLP) measurements are conducted right after exposure to 60Co gamma-ray up to 200 krad(Si). Besides, the TLP tests are performed at different temperatures ranging from 300 to 400 K to show the impact of elevated temperature on ESD devices. In the meanwhile, the physical mechanisms of the synergistic effects are investigated by means of three-dimensional (3D) TCAD simulations.

Design and Optimization of High-Failure-Current Dual-Direction SCR for Industrial-Level ESD Protection

In an industrial-grade bus, transient voltage suppressor (TVS) devices that need to withstand inrush currents ensure electrostatic discharge (ESD) reliability of the core chip. This article designs four types of dual-direction silicon-controlled rectifier (DDSCR) device structures based on the 0.5-μm CMOS process. The ESD performance of the TVS device is predicted and verified based on the basic principles of the device, two-dimensional device simulation, and transmission line pulse test results. Four DDSCR structures are embedded with floating N+ to adjust the device's holding voltage window. The results show that the current release capacity of DDSCR_1 is 81.93 mA/μm. The current release capability of DDSCR_2, which has a double-dummy-gate structure, is 82.37 mA/μm. The current release capability of DDSCR_3 of the gate-controlled structure is 86.68 mA/μm. The current release capability of DDSCR_4 of the double-dummy-gate structure and the gate-controlled structure is 86.25 mA/μm. Furthermore, the effect of the size of these devices on the ESD characteristics was studied. The on-resistance of the device structure is calculated by the curve-fitting method. The influence of the dummy gate structure and the gate-controlled structure on the ESD characteristics is analyzed. Finally, the optimal device size to meet the window is found.

Optimization of deep well gate-controlled dual direction SCR device for ESD protection in 0.5 μm CMOS process

Both traditional dual direction SCR (TDDSCR) and deep well gate-controlled dual direction SCR (DGC-DDSCR) are designed and fabricated in a 0.5 μm CMOS process. The ESD performance of the DDSCR device is predicted and verified by two-dimensional device simulation and transmission line pulse test results. The results show that when the TDDSCR changes the distance between the electrode N+ and the trigger surface P+(D4), the holding voltage increased from 10.1 V to 13.53 V, and the failure current remains stable (13.9A). The RS485 bus requires that the trigger voltage and the holding voltage of the ESD device be greater than 14.4 V, while TDDSCR is still unable to meet the on-chip ESD protection requirements for RS485 bus. However, when DGC-DDSCR increases the gate length (D4) of the anode and cathode, the holding voltage increases from 10.21 V to 15.18 V, and the failure current remains 14.63A. The test data has met the on-chip ESD protection requirements of the RS485 bus, and the size optimization problem of the DGC-DDSCR is discussed. The device has a strong current handling capability (91.25 mA/μm).

An ESD robust high holding voltage dual-direction SCR with symmetrical I-V curve by inserting a floating P+ in PWell

The dual directional silicon-controlled rectifier (DDSCR) device is widely used in on-chip electrostatic discharge (ESD) protection owing to its bi-directional ESD protection and strong current-tolerating capability per area. In this paper, an asymmetrical dual directional ESD protection device for automotive application was developed in a 0.18-µm Bipolar CMOS DMOS (BCD) technology. In order to verify and predict the proposed ESD protection device’s characteristics, a transmission line pulse (TLP) testing system and a 2-dimension device simulation platform have been used in this work. According to the measurement results, the asymmetrical dual directional silicon-controlled rectifier with a floating P+ region (ADDSCR_FP+) increases the forward holding voltage (Vh) from 3.89 V to 19.7 V and increases the reverse holding voltage from 3.62 V to 19.5 V which only slightly decrease the failure current compared with the traditional asymmetrical dual directional silicon-controlled rectifier (ADDSCR). The ADDSCR_FP+ has the features of symmetrical forward and reverse I-V curves, high holding voltage and high failure current.

Dual direction SCR with deep well structure for high voltage ESD in communication bus

In order to improve the robustness of the ESD of the dual-direction silicon-controlled rectifier, a low doping deep well PB structure is proposed instead of the traditional high doping P+ structure. The ESD stress of the dual-direction SCR devices with deep well structure is discharged from inside and the lattice temperature of the device is low to avoid premature burnout of the device. The deep well PB structure on the surface of the device increases the parasitic resistance of the device and improve the conduction uniformity of the device. As the main conduction path of the device is located in NBL, the PB structure does not have a large influence on the sustain voltage. It is verified in a 0.25 μm BCD process. With equivalent circuit and two-dimensional device simulation, the working mechanism is analyzed. According to the transmission line pulse test results and comparing with the data from traditional dual-direction SCR structure. The device’s fault current increases from 5.486 A to 8.13 A which is suitable for communication bus high voltage electrostatic discharge (ESD) protection.

A New Dual-Direction SCR With High Holding Voltage and Low Dynamic Resistance for 5 V Application

Dual-directional silicon-controlled rectifiers (DDSCRs), which provide both positive and negative electrostatic discharge (ESD) surge paths, are ESD protection devices with an excellent area efficiency. However, DDSCRs have a low holding voltage for use in 5 V-class applications, with a relatively high on-state resistance because of the elongated ESD surge path compared to unidirectional SCRs. In this paper, we propose a novel DDSCR with a higher holding voltage and a better ESD tolerance than conventional low-triggering DDSCRs (LTDDSCRs), realized by operating two additional parasitic bipolar transistors. The proposed ESD protection device was developed through a 0.18- $\mu \text{m}$ CMOS process, and a timeline pulse system was used to verify its properties. The measurement results show that the proposed ESD protection device exhibits an improved tolerance and a high holding voltage and is expected to be reliable in 5 V-class applications

A Novel High Holding Voltage Dual-Direction SCR With Embedded Structure for HV ESD Protection

In order to boost the holding voltage of the multi-fingered dual-direction silicon-controlled rectifier, a novel embedded topology is proposed instead of the traditional interdigital multi-finger arrangement. It is verified in a 0.5- $\mu \text{m}$ 18-V standard CDMOS process and applied to the high-voltage electro-static discharge (ESD) protection. With equivalent circuit and 2D device simulation, the operation principle and working mechanism are analyzed. According to the TLP-test results, the holding voltage of the multi-finger device is greatly improved from 7.62 V (traditional interdigital structure) to 19.67 V (the proposed embedded structure), and it has a narrower ESD design window (9.26 V) than that of the interdigital counterpart (15.17 V). Furthermore, the principle of the multi-finger device with embedded topology features a superior holding voltage is explained by using the model of ladder resistance network. It is concluded that the Ron of the embedded structure is determined by the size of topology and almost unaffected by the number of fingers.

Robust dual-direction SCR with low trigger voltage, tunable holding voltage for high-voltage ESD protection

An LDNMOS-based and an LDPMOS-based dual direction silicon controlled rectifier (DDSCR) devices have been designed and fabricated in a 0.5-μm 5V/18V high voltage (HV) CDMOS process. These devices can be used to protect pins with a voltage range that goes above and below the ground by discharging electrostatic current in both positive and negative directions. A 2-dimension (2D) device simulation and a transmission line pulse (TLP) measurement were used to predict and characterize the ESD performance of the two DDSCR devices. Compared to LDNMOS-based DDSCR, LDPMOS-based DDSCR is excellent for its relatively low trigger voltage of 33V and strong electrostatic discharge (ESD) current handling capability of 87mA/μm. Furthermore, the holding voltage of LDPMOS-based DDSCR can be elevated by tuning layout parameter. Such a device has been applied to I/O bus terminals of a data interface circuit for its on-chip ESD protection.

Study of current saturation behaviors in dual direction SCR for ESD applications

The current saturation behaviors of Dual Direction Silicon Controlled Rectifier (DDSCR) and N+ Modified Dual Direction SCR (NMDDSCR) are investigated under transmission line pulse (TLP) stress, compared with Unidirectional SCR (USCR). DDSCR and NMDDSCR are more prone to saturation current state due to different ESD discharge paths, which are verified by TCAD simulation. The saturation current behavior should be suppressed for better ESD effectiveness and robustness. By increasing the lengths of N+ and P+ diffusion area, the saturation current can be suppressed effectively.