Dual Control Gate Research Articles

A fast-switching low-loss field-stop IGBT with dual control gate of SIPOS material

A fast-switching low-loss field-stop insulated gate bipolar transistor with a dual control gate (DIGBT) of a semi-insulating polycrytalline silicon (SIPOS) material is proposed in this paper. Because the SIPOS has uniform high resistance, it has an approximate linear electric potential distribution. When DIGBT conducts, the higher electric potential on SIPOS causes the P-type drift region (P-drift) to generate an inversion layer of electrons, adjusting the number of carriers and making the generation of non-equilibrium carriers no longer dependent on the doping concentration in P-drift (Nd) but on the electric potential distribution on SIPOS. Therefore, it can solve the contradiction among the breakdown voltage, forward voltage drop [VCE(sat)], turn-off time (toff), and turn-off loss (Eoff) caused by the Nd. Through Technology Computer Aided Design (TCAD) simulation, the VCE(sat) of DIGBT is 30.6% lower than that of SJFS IGBT. Meanwhile, DIGBT reduces the toff by 62.8% while reducing the Eoff by 83.0% compared to SJFS IGBT. In addition, the static latch-up I–V and the forward biased safe operating area of the DIGBT have been significantly improved. This paper adjusts the number of carriers through the characteristics of SIPOS material, enabling the above-mentioned physical phenomena to be applied in insulated gate bipolar transistor power devices and achieving device performance breakthroughs.

Performance analysis of dual material control gate cavity on source electrically doped TFET biosensor for biomedical applications

The fabrication complexity, low sensitivity, detection speed, and costs associated with nanoscale devices have been significant concerns in the development of label-free biosensors. To address these issues, we report a novel dual material control gate cavity on source electrically doped tunnel field-effect transistor (DM-CG-CS-ED-TFET) for label-free biosensors. In this regard, the n+ drain and p+ source regions within the proposed device are induced by applying polarity gate (PG) bias voltages of PG-1 = +1.2 V and PG-2 = −1.2 V, respectively, across the respective polarity gate electrodes. This approach not only overcomes doping control issues but also avoids thermal budget constraints and minimizes fabrication complexity when compared to conventional TFET. For biomolecule sensing in the device, a nanogap cavity is created within the gate dielectric by selectively etching a portion of the polarity gate dielectric layer towards the source side. The performance of the proposed biosensor device is evaluated based on the variations in carrier concentration profile, energy band diagram, electric field, transfer (IDS - VGS) characteristics, drain current (IDS) sensitivity, ON-state current (ION) sensitivity, switching ratio (ION/IOFF) and subthreshold swing (SS) sensitivity. The sensitivity of the device is also investigated based on nano-cavity dimensions, practical challenges such as various filling factors, and the step profile generated from the steric hindrance. Moreover, the effect of temperature on sensitivity has also been investigated. For this, various biomolecules including Streptavidin (k = 2.1), APTES (k = 3.57), ferrocytochrome c (k = 4.7), keratin (k = 8) and Gelatin (k = 12), have been investigated for their performance using Silvaco ATLAS device simulator. The simulation results demonstrate that the proposed biosensor is a viable option for biosensing applications in biomedical engineering.

Low-K Dielectric Pocket and Workfunction Engineering for DC and Analog/RF Performance Improvement in Dual Material Stack Gate Oxide Double Gate TFET

In this paper, we investigate the effect of low K dielectric pocket on DC and analog/RF performance in dual material stack gate oxide double gate tunnel field effect transistor. For this, we have considered an optimized dielectric pocket at the interface of the source-channel tunneling junction to reduce the barrier width. A stack gate oxide (SiO2 + HfO2) with workfunction engineering is applied to improve the capacitive coupling, decrease the ambipolar, leakage currents and increase the ON-current (ION). In addition, the entire gate has been divided into three segments, named as tunnelling gate (M1) with workfunction (ϕ1), Control gate (M2) with workfunction (ϕ2) and auxiliary gate (M3) with workfunction (ϕ3). All the possible combinations of these workfunctions were considered to maintain dual work functionality. Further, technology computer-aided design (TCAD) simulations for these possible combinations were carried out and compared with single material stack gate oxide dual gate source dielectric pocket TFET (ϕ1 = ϕ2 = ϕ3). Simulation results shows that the workfunction combination (ϕ1 = ϕ3 < ϕ2) outperforms the other three structures. Further, the performance of this device is compared with dual material control gate source dielectric pocket TFET (DMCG-SDP-TFET) with SiO2 gate oxide. The dielectric pocket at the tunneling junction and workfunction engineering on the stack gate oxide shows significant enhancement in ON state current (1.47× 10− 4A/μm), ION/IOFF (3.14× 1012), point subthreshold slope (15.7mV/decade), transconductance (1.02× 10− 3S), cut-off frequency (1.93× 1011Hz) and significant changes in other analog/RF performance parameters, making this device suitable for high frequency and low power applications.

A Dielectric Modulated Biosensor for SARS-CoV-2

The manuscript proposes a novel dielectric modulated FET biosensor for the detection of SARS-CoV-2 in terms of spike, envelope and DNA proteins of the virus. The models used in a simulation and the transfer characteristic of the proposed sensor both are first calibrated with the fabricated FET sensor. Than the modification of low workfunction Hf Gate2 (dual metal control gate) has been proposed in the manuscript. The extended Hf Gate2 provides more space for immobilization of the virus proteins and utilize the advantages of charge plasma formation and electrical doping. In the manuscript, sensitivity of the proposed sensor has been investigated by DC and RF parameters in terms of virus proteins and their charge densities. In addition, a comparative analysis of the proposed sensor with and without Hf Gate2 has been examined in terms of DC/RF parameters that reveal a significance of the proposed modification. Moreover, the Impact of replacement of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> insulating layer by HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> has also been studied over the sensing ability of sensor in the context of DC/RF components.

Impact of Interface Trap Charges on Analog/RF and Linearity Performances of Dual-Material Gate-Oxide-Stack Double-Gate TFET

This paper investigates the impact of different interface trap charges (ITCs) on dual-material gate-oxide-stack double-gate TFET (DMGOSDG-TFET) by introducing localized charges (donor/acceptor) at the interface of semiconductor/insulator. For this, we have observed the effects of different ITCs on both conventional dual material control gate tunnel field effect transistor (DMCG-TFET) and dual-material gate-oxidestack double-gate TFET with identical dimensions in terms of DC, analog/RF and linearity performance parameters. Both the devices with positive (donor) and negative (acceptor) ITCs, have been simulated using technology computer-aided design (TCAD) tool. To understand the impact of different ITCs on the DC and analog/RF performances, the parameters such as electric field, transfer characteristics, transconductance, parasitic capacitance, fT, GBP and TFP for DMGOSDG-TFET have been analyzed and compared with that of DMCG-TFET. Further, to analyze the effect of different ITCs on the linearity performances, the parameters VIP2, VIP3, IIP3 and IMD3 have been investigated and compared with that of the conventional DMCG-TFET. Simulation results demonstrate that DMGOSDG-TFET is more immune towards different types of ITCs as compared to the conventional DMCG-TFET. Hence, DMGOSDG-TFET is more reliable over the conventional device for ultra low power applications.

Examination of the impingement of interface trap charges on heterogeneous gate dielectric dual material control gate tunnel field effect transistor for the refinement of device reliability

In this work, the authors have reported the reliability issues of dual material control gate tunnel field effect transistor (DMCG-TFET) and proposed heterogeneous gate dielectric dual metal control gate tunnel field effect transistors (HD DMCG-TFETs) in terms of interface trap charges (ITCs). The positive and negative types of localised charges at the semiconductor/insulator interface cause degradation in the device performance (DC/RF). In this regard, the proposed structure which includes combination of low-K and high-K dielectric improves the immunity towards the ITCs at the interface of semiconductor/insulator with better performance. In this concern, the study has analysed the impact of ITCs on DC and analogue/RF performances of the DMCG-TFET and HD DMCG-TFET in terms of various parameters like electric field, energy band diagram, carrier concentration, transfer characteristics, transconductance ( g m ), cutoff frequency ( f T ) and gain bandwidth product. Further to this, impact on device linearity parameters is also analysed through higher order of transconductance coefficients ( g m 3 ), VIP2, VIP3 and IIP3.

A Barrier Controlled Charge Plasma-Based TFET With Gate Engineering for Ambipolar Suppression and RF/Linearity Performance Improvement

To address the fabrication complexity and cost of nanoscale devices, a dual material control gate charge-plasma-based tunnel FET (DMCG-CPTFET) is presented for the first time for the suppression of ambipolarity and improvement of analog/radio frequency (RF), and linearity performance. The formation of p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> source and n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> drain regions in DMCG-CPTFET is done by the deposition of platinum (work-function = 5.93 eV) and hafnium (work-function = 3.9 eV) materials, respectively, over the silicon body. Hence, the proposed device avoids doping control issues, random dopant fluctuations, and it neither needs abrupt doping nor high thermal budget, which makes fabrication process simpler. In DMCG-CPTFET, the gate is divided into three segments, namely, tunneling gate (M <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ), control gate (M <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ), and auxiliary gate (M <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) with their equivalent work functions as φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> , φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , respectively. However, we have explored three different combinations of work-functions to achieve better performance in terms of DC, analog/RF, and linearity metrics. In various possibilities of devices, ATLAS device simulations show that the DMCG-CPTFET attains optimum result with φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> = φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> <; φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , where φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> is used at source side to improve the ON-state current, whereas φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (same as φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ) is considered at drain side in order to suppress the ambipolarity.

Investigation of gate material engineering in junctionless TFET to overcome the trade-off between ambipolarity and RF/linearity metrics

In this work, we investigate for the first time dual material control gate junctionless tunnel-field effect transistor (DMCG-JLTFET) to improve the metrics in terms of DC, analog/RF parameters, and linearity performance. In this regard, we have considered N-type heavily doped silicon and formation of P+ source and intrinsic region beneath gate are performed by work-function engineering (dual material) concept with the deposition of metal electrodes over the silicon body, while, the drain region and the gap between source and channel remains with its original N+ doping. This forms the P+-N+-I-N+ gated structure similar to pocket doped TFET and prevents the device from random dopant fluctuations (RDFs). The gate electrode used to form the intrinsic region is partitioned into three parts namely auxiliary gate (M1), control gate (M2), and tunnel gate (M3) with work-functions ϕM1, ϕM2 and ϕM3, respectively where (ϕM1 = ϕM3 < ϕM2). Appropriate work-functions for the gate electrodes (M1, M2 and M3) in DMCG-JLTFET are used to address the trade-off between the ambipolarity and RF/linearity parameters. It provides superior results in terms analog/RF and linearity performance as compared to other possible combinations.

Approach for ambipolar behaviour suppression in tunnel FET by workfunction engineering

A dual material control gate tunnel field effect transistor (TFET) for asymmetric doping at source and drain regions is proposed. The gate consists of three segment different workfunctions ϕ 1, ϕ 2, and ϕ 3, which are named as tunnelling gate (M 1), control gate (M 2), and auxiliary gate (M 3), respectively. Forward to this, three possible combinations of ϕ 1, ϕ 2 and ϕ 3 to maintain the dual workfunctionality of the device (ϕ 2 = ϕ 3 > ϕ 1, ϕ 1 = ϕ 2 > ϕ 3, ϕ 1 = ϕ 3 < ϕ 2) were considered. Further, the comparison of these possible combinations are performed with conventional TFET (ϕ 1 = ϕ 2 = ϕ 3). Among these ϕ 1 = ϕ 3 < ϕ 2, generates most optimum results in terms of suppression of ambipolar behaviour, and enhancement in ON state current (I ON) of the device. The proposed device shows significant improvement in terms of I ON (1.66 × 10−5 A/μm for SiO 2), I ON/I OFF (7.22 × 1011), and sub-threshold swing (∼19 mV/decade) as compared with conventional and the dual material TFET devices. Further, the analysis of analogue/RF performance is performed for the devices showing optimum performance in terms of suppression of ambipolar behaviour.

On the Investigation of a Novel Dual-Control-Gate Floating Gate Transistor for VCO Applications

A new MOS device called Dual-Control Gate Floating Gate Transistor (DCG-FGT) is used as a building block in analog design. This device offers new approaches in circuit design and allows developing new functionalities through two operating modes: Threshold Voltage Adjustable Mode, where the DCG-FGT behaves like a MOS transistor with an electrically adjustable threshold voltage. Mixer Signal Mode where the DCG-FGT can mix two independent signals on its floating gate. This device is developed to be fully compliant with CMOS Non Volatile Memory (NVM) process. An electrical model of the DCG-FGT has been implemented in an electrical simulator to be available for analog design. A DCG-FGT based ring oscillator is studied in this paper.

Advanced DC-SF Cell Technology for 3-D NAND Flash

Advanced dual control gate with surrounding floating gate (DC-SF) cell process and operation schemes are successfully developed for 3-D nand flash memories. To improve performance and reliability of DC-SF cell, new metal control gate last (MCGL) process is developed. The MCGL process can realize a low resistive tungsten (W) metal wordline, a low damage on tunnel oxide/inter-poly dielectric (IPD), and a preferable floating gate (FG) shape. Also, new read and program operation schemes are developed. In the new read operation, the higher and lower Vpass-read are alternately applied to unselected control gates to compensate lowering FG potential to be a pass transistor. In the new program scheme, the optimized Vpass are applied to neighbor WL of selected WL to prevent program disturb and charge loss through IPD. Thus, by using the MCGL process and new read/program schemes, the high performance and reliability of the DC-SF cell can be realized for 3-D nand flash memories.

A novel three-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell

A novel three-dimensional (3D) Dual Control gate with Surrounding Floating gate (DC-SF) NAND flash cell has been successfully developed. The DC-SF cell consists of a surrounding floating gate with stacked dual control gates. With this structure, high coupling ratio, low voltage cell operation, and wide P/E window (9.2V) can be obtained. Moreover, negligible FG–FG coupling interference (12mV/V) is achieved due to the control-gate shield effect. As a result, DC-SF NAND flash cell can overcome the problems of SONOS-based 3D NAND flash. It is proposed that 3D DC-SF NAND flash cell is the most promising candidate for 1Tb and beyond, with stacked multi bit FG cell (2–4bits/cell).

Dual-control-gate floating gate transistor: a building block for circuit design

A new circuit concept based on the use of a single floating gate transistor with a dual-control gate is presented. This device which is derived from a Flash memory cell, offers many possibilities for circuit design through two operating modes in straightforward manner: (i) the threshold voltage adjustable mode, where the dual-control-gate floating-gate transistor (DCG-FGT) behaves like a MOS transistor with an electrically adjustable threshold voltage, or (ii) a mixer signal mode where the DCG-FGT can mix two independent signals.

A new architecture of dual control gate EEPROM

A novel concept of dual control gate EEPROM (Electrically Erasable and Programmable Read-Only Memory) cell and array architecture are proposed. New programming conditions used for write and erase operations are developed to improve the lifetime of the cell. This approach allows a programming of the cell only by the top of the structure without bias on the drain-bulk or source-bulk junctions. Moreover, compared to the standard FLOating gate Tunnel OXide (FLOTOX) EEPROM, the select transistor has been eliminated, thus attaining a single transistor configuration so a high density memory cell. This EEPROM structure allows to program the cell with two different oxides for each charges transfer in the floating gate. In conventional EEPROM a single oxide is stressed during programming operations so with this new cell we reduce thin tunnel oxide degradations. A compact model shows that the basic functions of the EEPROM cell, namely reading, programming and erasing are possible with a suitable setting of the applied voltages. Scalability and endurance potentiality make this cell interesting for future high-density and high reliability applications.

Optimum design of dual-control gate cell for high-density EEPROM's

A new floating-gate-type cell with a dual-control gate (dc cell) has been developed and the structure optimized to realize high-density EEPROM's. In this new cell, an address selection transistor has been eliminated, thus attaining a single-transistor-per-cell configuration. The address selection is achieved by coincidence of two control gates, which are connected to column or row decoders supplied with an appropriate programming voltage. The stored charge in the floating gate suffers some disturbance by repetition of half-selection mode operation--defined as a state in which one of the control gates is set to high and the other to low during programming. In order to improve the endurance of the cell against half-selection mode operation, a new source biasing method has been introduced. As a result, the endurance has been improved by more than 3 orders of magnitude. A WRITE/ERASE endurance of 105cycles and a data retention capability of more than 10 years have been obtained for the dc cell. The design parameters for a 64K EEPROM chip are also described.