A new architecture of dual control gate EEPROM

Abstract

A novel concept of dual control gate EEPROM (Electrically Erasable and Programmable Read-Only Memory) cell and array architecture are proposed. New programming conditions used for write and erase operations are developed to improve the lifetime of the cell. This approach allows a programming of the cell only by the top of the structure without bias on the drain-bulk or source-bulk junctions. Moreover, compared to the standard FLOating gate Tunnel OXide (FLOTOX) EEPROM, the select transistor has been eliminated, thus attaining a single transistor configuration so a high density memory cell. This EEPROM structure allows to program the cell with two different oxides for each charges transfer in the floating gate. In conventional EEPROM a single oxide is stressed during programming operations so with this new cell we reduce thin tunnel oxide degradations. A compact model shows that the basic functions of the EEPROM cell, namely reading, programming and erasing are possible with a suitable setting of the applied voltages. Scalability and endurance potentiality make this cell interesting for future high-density and high reliability applications.