120 ns 128 k*8 b/64 k*16 b CMOS EEPROMs

Abstract

A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0- mu m triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 mu m*8 mu m, and the chip is 7.73 mm*11.83 mm. The device is configured as either 128 k*8 or 64 k*16 by a through-hole mask option. A 120-ns read access time has been achieved. The differential sensing scheme uses an output of the current sense amplifier connected to an unselected memory array as a reference level. The sense amplifier, the clock timing diagram, and the access waveform are shown, and typical process parameters are listed. >