Dual-band Low Noise Amplifier Research Articles

Dual-Band Low-Noise Amplifier for GNSS Applications

A new dual-band low-noise amplifier (LNA) operating at L1/E1 1.575 GHz and L5/E5 1.192 GHz center frequencies for global navigation satellite system receivers is proposed. A doubled common-source amplifier architecture is used with a single input, shared gate inductor, and two outputs to split the RF signal into separate RX channels. The main advantage of the proposed circuit is compatibility with widespread multi-band antennas with single RF connectors dedicated to high-precision applications, as well as the possibility to use cheap SAW filters with small footprints to build low-cost, highly accurate GNSS receiver modules. The input and both outputs are well matched to 50 Ω impedance. The LNA is designed with a 110 nm CMOS process, consuming 6.13 mA current from a 1.5 V supply. The measured noise figures and voltage gains of the dual-band LNA are, respectively, NF1/NF5 = 3.23/3.5 dB and G1/G5 = 21.22/18.2 dB in the band of interest for each channel. The measured impedance matching at the input (S11) and output (S22) of the dual-band low-frequency amplifier is as follows: S11_L1 = −23.89, S11_L5 = −8.42, S22_L1 = −12.65, S22_L5 = −15.08. The one-decibel compression points are L1 band PdB1 = −37.71 dBm and L5 band PdB5 = −34.72 dBm, respectively.

A High Gain Concurrent Dual-band Low-Noise Amplifier in 130-nm BiCMOS Technology

This paper presents a fully integrated concurrent 15/30-GHz dual-band low-noise amplifier (LNA). The proposed concurrent LNA IC is designed and simulated in 130-nm BiCMOS technology. The new passive LC notch filter is proposed to realize high gain and low noise figure over dual-band frequency, simultaneously. The simulated BiCMOS LNA IC has exhibited peak gains of 30.1/23.7 dB at 15/30-GHz, respectively, with 20-mW power consumption from 1-V supply. The concurrent dual-band LNA achieves noise figure of 2.2/2.9-dB and IIP3 of -18.2/-8.8 dBm at the respective passbands. Therefore, the proposed dual band concurrent LNA IC is applicable to front-end RF receivers for Ku-Band and Ka-Band systems.

High-Q Transformer Neutralization Technique for W-Band Dual-Band LNA Using 0.1 μm GaAs pHEMT Technology

In this study, a dual-band low-noise amplifier (LNA) was implemented by applying a transformer-based neutralization technology to the W-band. Incorporating the neutralization technique was difficult owing to performance degradation in the W-band. However, circuit performance was enhanced thanks to the layout optimization of transformer-based neutralization networks, and the improved operation was confirmed in the W-band. The neutralization technique was implemented in four stages with a 0.1-μm gallium arsenide (GaAs) pseudomorphic high-electron-mobility-transistor monolithic microwave integrated circuit LNA. The LNA showed small signal gains of 20.3 dB and 21.7 dB and noise figures of 5.0 dB and 6.4 dB (at 84 GHz and 96 GHz, respectively) while consuming 46 mW from a 1-V supply.

A 39/48 GHz Switchless Reconfigurable Low Noise Amplifier Using Common Gate and Coupled-Line-Based Diplexer

This paper presents a switchless dual-band low-noise amplifier (LNA) that can be reconfigured to include n260 (37.40 GHz) and n262 (47.2.48.2 GHz) millimeter-wave (mm-Wave) dual bands. The proposed reconfigurable LNA is designed to separate and isolate two bands, using a common gate and coupled-line-based diplexer for the inter-stage of cascade amplifiers. A common gate amplifier has the advantage of simultaneously selecting the signal path and amplifying the signal power according to a band, using an impedance variation between the gon/offh conditions of gate bias. In addition, the coupled-line-based diplexer can be optimized to exhibit high isolation characteristics between frequencies using high and low-pass characteristics. The designed reconfigurable LNA is fabricated with the 0.15–μm GaAs pHEMT process. With the high frequency (HF) mode, the reconfigurable LNA achieves a measured gain of 19.2 dB at the center frequency, noise figure, and OP1dB of 48 GHz, 4.8 dB, and 6.88 dBm, respectively. In the low frequency (LF) mode, the reconfigurable LNA exhibits a measured gain of 24.8 dB at the center frequency, noise figure, and OP1dB of 39 GHz, 3.9 dB, and 6.80 dBm, respectively. The chip occupies a core area of 3.04 mm2, which consumes 61.4 mW and 64.7 mW in the HF and LF modes, respectively.

Frequency-Reconfigurable Dual-Band Low-Noise Amplifier With Interstage Gm-Boosting for Millimeter-Wave 5G Communication

A differential low-noise amplifier (LNA) for the 5G n257 band and a frequency reconfigurable differential LNA for both the 5G n257 and n260 bands (26.5–29.5 and 37–40 GHz), fabricated in a 65-nm CMOS process, are presented. Both LNAs achieve better gain and noise figure performances due to the use of magnetically coupled gm-boosting in the common-gate stage of a cascode amplifier. Furthermore, the frequency-reconfigurable LNA uses frequency reconfigurable matching circuits at the input, interstage, and output to achieve optimal noise and gain matchings for each band. The single band LNA has a core chip area of 0.11 mm2, a peak gain of 11.9 dB, a 3-dB bandwidth of 5.3 GHz, and a noise figure of 2.79 dB at 28.5 GHz. The dual-band LNA is capable of dual-band operation due to the reconfiguring matching circuits with switched coupled inductors (SCIs) and switched capacitors. It has a core chip area of 0.12 mm2, peak gains of 11.1/8.5 dB, 3-dB bandwidths of 4.8/9.4 GHz, and minimum noise figures of 3.49/4.01 dB at 28.5/38 GHz, respectively.

A 28-/39-GHz Dual-Band CMOS LNA With Shunt-Series Transformer Feedback

This letter presents a concurrent dual-band low-noise amplifier (LNA) operating at 28 and 39 GHz for multiband 5G wireless systems. In order to achieve a wideband input power matching, the LNA adopts a shunt-series feedback structure. Detailed noise analysis of the shunt-series transformer feedback LNA is proposed to guide the noise-optimized design, and a modified input network is proposed to improve the noise matching. The modified method also enhances the transconductance of the input stage, thus suppressing the noise of the subsequent circuit and obtaining a better overall noise figure (NF). Based on this input structure, a dual-band LNA with excellent NF is designed in a 65-nm complimentary metal–oxide–semiconductor (CMOS) process. This dual-band LNA achieves 18.1/18.4-dB gain and 3.1/3.8-dB NF at 28/39 GHz, consuming 10.2 mW from a 1.0-V power supply.

A concurrent dual-band low noise amplifier with gain enhancement topology for 2.4/5.2 GHz applications

本文提出了一种工作在2.4 / 5.2GHz的双频谱低噪声放大器（LNA），用于无线链接（WLAN）应用。 刚刚采用了一个具有L转换的小型电容器来实现增益增强。 同时，使用LC并行仿真 结果表明，LNA的增益（S21）为17.1dB和8.5dB，在2.4GHz和5.2GHz时的噪声系数分别为3.6dB和3.3dB，而输入回波损耗（S11）则为-15.6dB和-13.8dB。可以研磨，在两个工作频率下的输出回波损耗（S22）分别为-11.7dB和-20.7dB，在上述两个宽带中，工作电压为1.2V的电路绝对稳定。

Design and analysis of a 1.1 and 2.4 GHz concurrent dual-band low noise amplifier for multiband radios

This paper presents the design and implementation of a dual-band low noise amplifier (DBLNA) operating at 1.1 GHz and 2.4 GHz. The DBLNA employs a second-order dual-band matching network, which is designed using the proposed impedance and frequency transformation technique. The DBLNA has two stages in cascade topology for its high output impedance and high voltage gain. Modified output load is designed to optimize interference rejection. The implemented circuit is fabricated as a microwave integrated circuit (MIC) on the FR-4 substrate. The designed DBLNA achieves a very high measured voltage gain of 24.4 dB and 20.1 dB at 1.1 GHz and 2.4 GHz, respectively. The measured NF of the DBLNA is 2.6 dB and 3 dB at 1.1 GHz and 2.4 GHz, respectively. The interference rejection between passbands at 1.6 GHz is 53.2 dB and stopband rejection ratio is 40.4 dB. The LNA consumes 108 mW from a 3 V supply. The measured P1dB performance is −10 dBm and −5.1 dBm at 1.1 GHz and 2.4 GHz, respectively.

Concurrent Dual-Band Inverter-Based Low Noise Amplifier (LNA) for WLAN Applications

low noise amplifier (LNA); concurrent; dual-band; inverter-basedIn this paper, a two-stage concurrent dual-band low noise amplifier (DB-LNA) operating at 2.4/5.2-GHz is presented for Wireless Local Area Network (WLAN) applications. The current-reused structure using resistive shunt-shunt feedback is employed to reduce power dissipation and achieve a wide frequency band from DC to-5.5-GHz in the inverter-based LNA. The second inverter-based stage is employed to increase the gain and obtain a flat gain over the frequency band. An LC network is also inserted at the proposed circuit output to shape the dual-band frequency response. The proposed concurrent DB-LNA is designed by RF-TSMC 0.18-µm CMOS technology, which consumes 10.8 mW from a power supply of 1.5 V. The simulation results show that the proposed DB-LNA achieves a direct power gain (S 21 ) of 13.7/14.1 dB, a noise figure (NF) of 4.2/4.6 dB, and an input return loss (S 11 ) of −12.9/−14.6 dBm at the 2.4/5.2-GHz bands.

Dual Q/V-Band SiGe BiCMOS Low Noise Amplifiers Using Q-Enhanced Metamaterial Transmission Lines

This brief presents two dual-band low noise amplifiers (LNAs) in Q/V-band fabricated in 0.18-μm SiGe BiCMOS technology. The developed LNAs function over the dual (44/60 GHz)-band with an integrated filtering function and achieve peak power gain of 19.1 dB with minimal gain imbalance of less than 0.2 dB between the two bands. The achieved 3-dB bandwidths are more than 6 GHz for each band of the two LNAs with the lowest measured noise figure of 5.6 dB in the targeted frequency bands. The synthesized Q-enhanced metamaterial transmission line structures proposed in this brief contribute a dual-band operation at 44/60 GHz with a rejection of more than 30 dB between the two bands. The Colpitts style negative generation circuit is utilized in conjunction with composite right/left-handed metamaterial transmission line and its dual structure, which is unprecedented, to realize multi-band millimeter-wave integrated circuits.

Co-design Structure of Dual-Band LNA and Dual-Band BPF for Radio Navigation Aid Application

In this paper, a co-design of a dual-band low-noise amplifier (DB-LNA) with a dual-band band-pass filter (DB-BPF) for a radio navigation aid (RNA) application was proposed. The novel development was that the DB-LNA was directly integrated with the DB-BPF instead of connecting the output matching network (OMN) of the DB-LNA to the 50 Ω-port of the DB-BPF. Thus, this DB-BPF had a double function, serving as the DB-BPF and also as the OMN. This architecture was called the co-design structure. ZIN analysis was used to evaluate the co-design network structure. In general, the design procedure was divided into four sections, including (1) DB-BPF, (2) DB-LNA, (3) Cascade DB-LNA and DB-BPF, and (4) Co-design DB-LNA and DB-BPF. The co-design method was applied in an RNA implementation at dual-band frequencies of 113 MHz and 332 MHz. Validation of the proposed structure is confirmed for its accuracy by simulating the impedance characteristic ZIN, S parameter simulation, and measurement results. The key contributions of this paper were that: (1) The co-design structure could reduce the passive component by 31.5%, (2) the total size of the DB-LNA and DB-BPF using the co-design method was smaller than the cascaded method by 11.36%, (3) more light-weight in fabrication due to a smaller size, and (4) finally, the proposed LNA has a higher figure of merit than the other LNA.

AKa/VBand-Switchable LNA With 2.8/3.4 dB Noise Figure

A 0.13 μm SiGe BiCMOS band-switchable low noise amplifier (LNA) is developed which can be operated at 28 or 60 GHz. The LNA employs an LC tank at the input to perform dualband impedance matching, while the output is switched from one band to the other using a tunable stub. The stub is made tunable by using an HBT switch, which reduces the stub's length when turned on shifting the LNA between 28 and 60 GHz modes. The switch has 1.2 dB ONand 0.7 dB OFF-state losses. The measured results are /15 dB small signal gain, 2.8/3.4 dB noise figure, and -12/-7 dBm compression point (P1dB) at 28/60 GHz, respectively. The band-switchable compact LNA has a chip size of 0.48 × 0.48 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes a dc power of 8.2/21 mW at 2.5 V supply voltage. Among the research studies, this is the first demonstration of a 28/60 GHz dual-band LNA with a performance comparable to dedicated LNAs in each band.

Analytical Noise Optimization of Single-/Dual-Band MOS LNAs With Substrate and Metal Loss Effects of Inductors

Analytical noise formulations and design optimization of single- and dual-band inductively source-degenerated MOS low-noise amplifiers (LNAs) with the substrate and metal loss effects of on-chip inductors are established in this paper. It reveals that the noise figures of both single-/dual-band LNAs degrade substantially under the consideration of the loss effects. However, by increasing the device size, the noise optimization methodology of simultaneous noise and input match for a single-band LNA still holds true with concern for the loss effects. For a dual-band LNA, analytical noise optimization for a balanced noise design is established for inductors with metal and substrate loss and indicates a larger device size. The substrate and metal loss effects of inductors can be mitigated using integrated passive device (IPD) process for the input match network. The demonstrated single-band 0.18- $\mu \text{m}$ MOS LNAs with and without IPD process show noise figures of 1.53 and 2.52 dB at 2.4 GHz, respectively. Subsequently, the implemented dual-band 0.18- $\mu \text{m}$ MOS LNAs with and without IPD process show noise figures of 1.6/2.6 and 3.25/4.1 dB at 2.4/5 GHz, respectively.

A 0.7/1.1-dB Ultra-Low Noise Dual-Band LNA Based on SISL Platform

This paper presents an ultra-low noise concurrent 2.45-/5.25-GHz dual-band low-noise amplifier (LNA) based on a substrate integrated suspended line (SISL) platform. This is the first LNA design in the SISL platform. To achieve optimal noise and power gain at both bands, the transition part of this SISL LNA is modeled and optimized to work with the matching networks consisting of $LC$ components and transmission lines. The SISL platform has the merits of high performance, low loss, and low cost with the standard print circuit board process. With the proposed technique, the dedicated LNA demonstrates the advantages of self-packaging, compact size, ultra-low noise figure of 0.7/1.1 dB, and rather high power gain of 28.4/28.8 dB at 2.45/5.25 GHz, respectively.

A Reconfigurable Dual-Frequency Narrowband CMOS LNA Using Phase-Change RF Switches

This paper presents a dual-band low-noise amplifier (LNA) that can be reversibly configured between 3 and 5 GHz using a phase-change (PC) RF switch. Simultaneous noise and conjugate input matching is achieved at the two frequencies using a single PC RF switch and coupled source inductors, thereby minimizing integration complexity and enabling a compact design roughly equal in size to a single-band design. The PC switch has extremely low on-state resistance (1.5– $4\Omega$ ) and parasitic capacitance (12–16 fF), and has a compact footprint ( $\sim 50~\mu \text{m}^{2}$ ). A chip containing the PC switch is fabricated in-house while the rest of the LNA is fabricated in a 0.13- $\mu \text{m}$ CMOS technology. The two chips are combined using an in-house flip-chip integration process. Characterization from five prototypes fabricated in two batches is presented. The integrated LNAs achieved peak gain greater than 20 dB and minimum noise figure less than 2.9 dB in both the frequency bands while consuming a peak power of 7.2 mW from a 1.2-V supply. Comparison of the CMOS-PC prototypes with carefully designed control LNAs demonstrates the effectiveness of the PC switch for RF reconfiguration, which allows the reconfigurable LNA to achieve performance comparable to its nonreconfigurable counterparts.

A 0.9–5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration

A 0.9–5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as the interface between the LNTA and the mixer features current-gain boosting in addition to wideband operation. Automatic local oscillator phase-error detection and calibration circuitry is implemented for the mixers to achieve high HR ratio (HRR). Fabricated in 65-nm CMOS, the RFE measures the noise figure between 2.9 and 3.8 dB, the third-order input intercept point (IIP3) between −1.6 and −12.8 dBm, the third-order HRR of 81 dB, and the fifth-order HRR of 70 dB, while consuming 66–82 mA from a 1.2-V supply and occupying a chip area of 4.2 mm2.

A 2.4/5.2-GHz Concurrent Dual-Band CMOS Low Noise Amplifier

A concurrent dual-band low-noise amplifier (LNA) targeted for W-LAN IEEE 802.11 a/b/g standards is designed using 0.13- $\mu \text{m}$ CMOS process. To attain the power-constrained simultaneous noise and input matching at 2.4 and 5.2 GHz, cascode common source inductive degeneration topology is adopted. The LNA achieves input reflection coefficients of −16.8 and −19.4 dB, forward gains of 19.3 and 17.5 dB at 2.4 and 5.2 GHz, respectively. Furthermore, the LNA exhibits noise figures of 3.2 and 3.3 dB with input 1-dB compression points of −29.6 and −28.2 dBm, while third-order input intercept points of −20.1 and −18.1 dBm at 2.4 and 5.2 GHz, respectively. The LNA dissipates 2.4 mW of power from a 1.2-V supply.

Triple-Band CMOS Low Noise Amplifier Design Utilizing Transformer Couplings

This paper describes multi-band low noise amplifiers (LNAs) utilizing input matching transformers. We investigate a conventional dual-band LNA circuit utilizing a transformer, and show our analysis and simulation results for its circuit. Based on this, we propose a triple band LNA with transformers. We have calculated characteristics of the dual-band and triple-band LNAs. As the results, the LNAs show gain of 20dB while maintaining good input matching, in the frequencies at 2.59GHz, 3.50GHz and 5.41 GHz. Then we discuss configuration and design of coupling coefficients of the transformers.

A Concurrent Dual-Band Low Noise Amplifier for GNSS Receivers

A Concurrent Dual-Band Low Noise Amplifier for GNSS Receivers

Systematic Determination of Limits on Noise Figure and Distortion in Power Constrained Capacitive Desensitized CMOS LNAs

ABSTRACTA systematic and generic approach is proposed to determine the minimum noise figure (NF), minimum second- and third-order harmonic distortion (HD2, HD3), and maximum input third-order intercept point (IIP3), achievable in a class of power constrained common source inductively degenerated low noise amplifiers (LNAs) using capacitance desensitization with and without multiple gated transistors. This is verified in complementary metal oxide semiconductor (CMOS) 180 nm technology. A Volterra series method is adopted to obtain closed-form expressions for both second- and third-order non-linearity. For validation, this analysis is applied to a highly linear single band LNA at 1.8 GHz and a linear dual band LNA at 2.8/3.4 GHz and corresponding limits on IIP3 and NF are established. To the best of the authors’ knowledge for the first time, such quantitative limits for obtaining a simpler design trade-off have been presented to the LNA design community.