Systematic Determination of Limits on Noise Figure and Distortion in Power Constrained Capacitive Desensitized CMOS LNAs

Abstract

ABSTRACTA systematic and generic approach is proposed to determine the minimum noise figure (NF), minimum second- and third-order harmonic distortion (HD2, HD3), and maximum input third-order intercept point (IIP3), achievable in a class of power constrained common source inductively degenerated low noise amplifiers (LNAs) using capacitance desensitization with and without multiple gated transistors. This is verified in complementary metal oxide semiconductor (CMOS) 180 nm technology. A Volterra series method is adopted to obtain closed-form expressions for both second- and third-order non-linearity. For validation, this analysis is applied to a highly linear single band LNA at 1.8 GHz and a linear dual band LNA at 2.8/3.4 GHz and corresponding limits on IIP3 and NF are established. To the best of the authors’ knowledge for the first time, such quantitative limits for obtaining a simpler design trade-off have been presented to the LNA design community.