DSP Applications Research Articles

Compressor tree synthesis on commercial high-performance FPGAs

Compressor trees are a class of circuits that generalizes multioperand addition and the partial product reduction trees of parallel multipliers using carry-save arithmetic. Compressor trees naturally occur in many DSP applications, such as FIR filters, and, in the more general case, their use can be maximized through the application of high-level transformations to arithmetically intensive data flow graphs. Due to the presence of carry-chains, it has long been thought that trees of 2- or 3-input carry-propagate adders are more efficient than compressor trees for FPGA synthesis; however, this is not the case. This article presents a heuristic for FPGA synthesis of compressor trees that outperforms adder trees and exploits carry-chains when possible. The experimental results show that, on average, the use of compressor trees can reduce critical path delay by 33% and 45% respectively, compared to adder trees synthesized on the Xilinx Virtex-5 and Altera Stratix III FPGAs.

A fast final adder for a 54-bit parallel multiplier for DSP application

A novel redundant binary-to-natural binary converter circuit is proposed which is used in the final addition stage of parallel multipliers. Use of this circuit in the final adder stage proves to be 17% faster than carry-look-ahead implementation. We used this algorithm in such a way that no redundant binary adder is required in compressing partial product rows. Only the natural 4:2 compressor circuits are used.

Rapid Control Prototyping Design of DSP-Based Motion Controller

This paper presents a Rapid Control Prototyping (RCP) development platform based on Matlab/Simulink, Real-Time Workshop and Embedded Target for C2000 and DSP development board. It also designs TMS320F2812 DSP-based motion controller under the proposed RCP. The controller using saturated integral PID algorithm produces PWM signal to control DC motor. Experimental results show that the designed controller can control motor accurately. Engineers can complete all design tasks such as modeling, automatic code generation, and download, running and parameters adjustment on this RCP platform when developing DSP application system. Thus the proposed RCP can shorten the DSP development cycle and improve the portability and modularity of program.

Guided Probabilistic Checksums for Error Control in Low-Power Digital Filters

In many DSP applications (image and voice processing), several dBs of SNR loss can be tolerated without noticeable impact on application level performance. For power optimization in such applications, voltage overscaling (VOS) can be used to operate the arithmetic circuitry at or marginally below the critical circuit path delay while incurring tolerable SNR loss due to the resulting periodic errors in computation. In this paper, low cost checksum codes are used for detection and compensation of intermittent errors due to voltage overscaling in linear digital filters. In traditional coding theory, diagnosis of errors is a key problem and incurs significant computation and latency cost. In the proposed approach, low-precision shadow latches are used to identify likely sources of errors due to voltage overscaling to avoid error diagnosis. This allows accurate error compensation with distance-2 checksum codes that are normally good only for error detection but not for correction. Very precise compensation is achieved by distributing the negative of the error value evenly across only the likely erroneous states. This is called guided probabilistic compensation, as compensation is not exact when errors occur simultaneously in more than one state. A feedback controller is used for dynamic voltage overscaling (DVOS) while keeping the error rate in the system within an acceptable range. It is shown that the low cost accurate error compensation allows significant power savings with minimal degradation in system performance (SNR).

Automatic PMD Compensation Based on GTPSO Algorithm in Optical Fiber Communication Systems

We demonstrate a universal DSP application for adaptive polarization mode compensation (PMD) compensation utilizing GTPSO algorithm in optical transmission systems. An adaptive PMD compensation experiment is implemented in an 80G/s DQPSK system. We designed a low power-consume DSP-based integrated control system to complete first-order PMD and second-order PMD compensation. The searching process and the tracking process for automatic PMD compensation could be completed in less than 10ms and 1ms.

Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware

In recent years, parameterized dataflow has evolved as a useful framework for modeling synchronous and cyclo-static graphs in which arbitrary parameters can be changed dynamically. Parameterized dataflow has proven to have significant expressive power for managing dynamics of DSP applications in important ways. However, efficient hardware synthesis techniques for parameterized dataflow representations are lacking. This paper addresses this void; specifically, the paper investigates efficient field programmable gate array (FPGA)-based implementation of parameterized cyclo-static dataflow (PCSDF) graphs. We develop a scheduling technique for throughput-constrained minimization of dataflow buffering requirements when mapping PCSDF representations of DSP applications onto FPGAs. The proposed scheduling technique is integrated with an existing formal schedule model, called the generalized schedule tree, to reduce schedule cost. To demonstrate our new, hardware-oriented PCSDF scheduling technique, we have designed a real-time base station emulator prototype based on a subset of long-term evolution (LTE), which is a key cellular standard.

A new FPGA architecture suitable for DSP applications

A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 μm CMOS technology successfully. The die size is 6.3 × 4.5 mm2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs.

A RISC architecture for 2DLNS-based signal processing

The multi-dimensional logarithmic number system (MDLNS) provides a reduction in the size of the number representation and promises a lower cost realisation of arithmetic operations. The non-linear nature of the representation and independency of the parallel-based computations combined with multi-digit extensions of the MDLNS representations along with simplified arithmetic operations, make MDLNS suitable for some multiplication intensive DSP applications. The work presented in this paper is the design and implementation of a 2DLNS-based processor architecture. This CPU takes advantage of a relatively simple architecture and a well designed organisation which greatly improves the implementation of many DSP algorithms. An assembly programme is also written to implement a 2DLNS-based filterbank architecture. This implementation demonstrates the efficiency and ease of use of 2DLNS CPU in real applications.

Remotely Controlled Real-Time DSP Applications through Customized GUIs based on LabVIEW

Remotely Controlled Real-Time DSP Applications through Customized GUIs based on LabVIEW

The Algorithm Research of Coin Detection Based on DSP

With the widespread using of coins, in order to solve the troubles brought by counterfeit money, it is of great significance to develop a system for real-time identification of coins. In the analysis of image processing technology, the hardware and software in this field, this paper has verified the recognition algorithm in the MATLAB and VC, and it had set up an coin image processing system with the DSP chip as a platform. In this system not only the surface information of the coin can be achieved and processed in real time, but also a practical hardware and software basis for the further application of DSP for image processing can be built.

Low power and high speed multiplier design with row bypassing and parallel architecture

This paper presents a low power and high speed row bypassing multiplier. The primary power reductions are obtained by tuning off MOS components through multiplexers when the operands of multiplier are zero. Analysis of the conventional DSP applications shows that the average of zero input of operand in multiplier is 73.8 percent. Therefore, significant power consumption can be reduced by the proposed bypassing multiplier. The proposed multiplier adopts ripple-carry adder with fewer additional hardware components. In addition, the proposed bypassing architecture can enhance operating speed by the additional parallel architecture to shorten the delay time of the proposed multiplier. Both unsigned and signed operands of multiplier are developed. Post-layout simulations are performed with standard TSMC 0.18μm CMOS technology and 1.8V supply voltage by Cadence Spectre simulation tools. Simulation results show that the proposed design can reduce power consumption and operating speed compared to those of counterparts. For a 16×16 multiplier, the proposed design achieves 17 and 36 percent reduction in power consumption and delay, respectively, at the cost of 20 percent increase of chip area in comparison with those of conventional array multipliers. In addition, the proposed design achieves averages of 11 and 38 percent reduction in power consumption and delay with 46 percent less chip area in comparison with those counterparts for both unsigned and signed multipliers. The proposed design is suitable for low power and high speed arithmetic applications.

A 12-kVA DSP-Controlled Laboratory Prototype UPQC Capable of Mitigating Unbalance in Source Voltage and Load Current

This paper reports the development of a laboratory prototype of a fully digital DSP-controlled 12-kVA unified power quality conditioner (UPQC), capable of compensating for both the supply voltage and the load current imperfections. A fully digital controller based on the TMS320F2812 DSP platform is implemented for the reference generation as well as control purposes. The delay problem in the digital controller is overcome by application of a fast DSP, a compact control technique and proper flow of control steps in the DSP software. A phase-locked loop-less software grid synchronization method has been implemented for the effective operation of the UPQC under conditions of grid frequency variation. A sequence-based compensation strategy has been developed to compensate for balanced and unbalanced sags while accommodating the fact that the voltage injection capability of the UPQC is limited. The prototype UPQC power circuit, control features, and control algorithm along with experimental results are presented in this paper.

Power Estimation of Embedded Multiplier Blocks in FPGAs

The use of embedded multiplier blocks has become a norm in DSP applications due to their high performance and low power consumption. However, as their implementation details in commercial field-programmable gate arrays are not available to users, and the power estimates given by the tested low-level tool are not accurate enough to validate high-level models, the work on power estimation of these blocks is very limited. We present a dynamic power estimation methodology for the embedded multipliers in Xilinx Virtex-II Pro chips. The methodology is an adaptation of an existing power estimation method for lookup-table-based components and uses information about the type of architecture of the embedded block. The power model is characterized and verified by on-board measurements and is ready for integration with high-level power optimization techniques. The experimental results show that the average accuracy of the model is higher than the average accuracy of the low-level commercial tool.

An efficient code update scheme for DSP applications in mobile embedded systems

DSP processors usually provide dedicated address generation units (AGUs) to assist address computation. By carefully allocating variables in the memory, DSP compilers take advantage of AGUs and generate efficient code with compact size and improved performance. However, DSP applications running on mobile embedded systems often need to be updated after their initial releases. Studies showed that small changes at the source code level may significantly change the variable layout in the memory and thus the binary code, which causes large energy overheads to mobile embedded systems that patch through wireless or satellite communication, and often pecuniary burden to the users. In this paper, we propose an update-conscious code update scheme to effectively reduce patch size. It first performs incremental offset assignment based on a recent variable coalescing heuristic, and then summarizes the code difference using two types of update primitives. Our experimental results showed that using update-conscious code update can greatly improve code similarity and thus reduce the update script sizes.

Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis

Multimedia applications such as video and image processing are often characterized as computation intensive applications. For these applications the word-length of data and instructions is different throughout the application. Generating hardware architectures is not a straightforward task since it requires a deep word-length analysis in order to properly determine what hardware resources are needed. In this paper we suggest an automated design methodology based on high-level synthesis which takes care of data word-length and interconnection resource cost in order to generate area and power efficient fixed-point architectures for DSP applications. Both ASIC and FPGA technologies are targeted. Experimental results show that our proposed approach reduces area by 6% to 42% on FPGA technology and by 9% to 48 % on ASIC compared to previous approaches. Power saving can reach up to 44% on FPGA technology and 36% on ASIC.

FPGA Based Hardware Co-Simulation of an Area and Power Efficient FIR Filter for Wireless Communication Systems

“In this paper FPGA based hardware co-simulation of an area and power efficient FIR filter for wireless communication systems is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with look up table (LUT) accesses. Parallel Distributed arithmetic (PDA) look up table approach is used to implement an FIR Filter taking optimal advantage of the look up table structure of FPGA using VHDL. The proposed design is hardware co-simulated using System Generator10.1, synthesized with Xilinx ISE 10.1 software, and implemented on Virtex-4 based xc4vlx25-10ff668 target device. Results show that the proposed design operates at 17.5 MHz throughput and consumes 0.468W power with considerable reduction in required resources to implement the design as compared to Coregen and add/shift based design styles. Due to this reduction in required resources the proposed design can also be implemented on Spartan-3 FPGA device to provide cost effective solution for DSP and wireless communication applications.”

Improving FPGA Performance for Carry-Save Arithmetic

The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed through systematic data flow transformations that can be applied by a hardware compiler. Field-programmable gate arrays (FPGAs), however, are not particularly well suited to carry-save arithmetic. To address this concern, we introduce the ?field programmable counter array? (FPCA), an accelerator for carry-save arithmetic intended for integration into an FPGA as an alternative to DSP blocks. In addition to multiplication and multiply accumulation, the FPCA can accelerate more general carry-save operations, such as multi-input addition (e.g., add k > 2 integers) and multipliers that have been fused with other adders. Our experiments show that the FPCA accelerates a wider variety of applications than DSP blocks and improves performance, area utilization, and energy consumption compared with soft FPGA logic.

Hardware/Software Co-reconfigurable Instruction Decoder for Adaptive Multi-core DSP Architectures

A programmable instruction decoder (PID) is introduced for designing adaptive multi-core DSP architectures by using a hardware/software co-reconfigurable approach without employing programmable devices. This PID permits DSP software developers for post-manufacturing modification of their DSP instruction sets to add their application-specific instructions whenever necessary. In addition, PID offers software developers an enhanced means to utilize the underlying DSP architectures by rescheduling implemented micro-operations for their tailored instructions in the DSP processors. Thus, emerging DSP applications can be swiftly and efficiently re-imported to PID-based DSP processors without re-fabrication of new DSP chips. In addition to instruction-level modification, an innovative instruction-packing procedure for PID is presented for further enhancement of the PID-based DSP systems. PID architecture was developed and implemented in VHDL. The PID-based DSP systems were also developed and evaluated to demonstrate various post-manufacturing adaptabilities in DSP processor systems. Various multi-core DSP architectures based on Texas Instruments' TMS320C55 DSP processor were used for evaluating performance and adaptability of this new programmable instruction decoder.

Buffer Sizing for Rate-Optimal Single-Rate Data-Flow Scheduling Revisited

Single-Rate Data-Flow (SRDF) graphs, also known as Homogeneous Synchronous Data-Flow (HSDF) graphs or Marked Graphs, are often used to model the implementation and do temporal analysis of concurrent DSP and multimedia applications. An important problem in implementing applications expressed as SRDF graphs is the computation of the minimal amount of buffering needed to implement a static periodic schedule (SPS) that is optimal in terms of execution rate, or throughput. Ning and Gao [1] propose a linear-programming-based polynomial algorithm to compute this minimal storage amount, claiming optimality. We show via a counterexample that the proposed algorithm is not optimal. We prove that the problem is, in fact, NP-complete. We give an exact solution, and experimentally evaluate the degree of inaccuracy of the algorithm of Ning and Gao.

Polyphase FIR Networks Based on Frequency Sampling for Multirate DSP Applications

It is well known that the frequency sampling approach to the design of Finite Impulse Response digital filters allows recursive implementations which are computationally efficient when most of the frequency samples are integers, powers of 2 or null. The design and implementation of decimation (or interpolation) filters using this approach is studied herein. Firstly, a procedure is described which optimizes the tradeoff between the stopband energy and the deviation of the passband from the ideal filter. The search space is limited to a small number of samples (in the transition band), imposing the condition that the resulting filter have a large number of zeros in the stopband. Secondly, three different structures to implement the decimation (or interpolation) filter are proposed. The implementation complexity, i.e., the number of multiplications and additions per input sample, are derived for each structure. The results show that, without taking into account finite word-length effects, the most efficient implementation depends on the filter length to decimation (or interpolation) ratio.