Abstract
“In this paper FPGA based hardware co-simulation of an area and power efficient FIR filter for wireless communication systems is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with look up table (LUT) accesses. Parallel Distributed arithmetic (PDA) look up table approach is used to implement an FIR Filter taking optimal advantage of the look up table structure of FPGA using VHDL. The proposed design is hardware co-simulated using System Generator10.1, synthesized with Xilinx ISE 10.1 software, and implemented on Virtex-4 based xc4vlx25-10ff668 target device. Results show that the proposed design operates at 17.5 MHz throughput and consumes 0.468W power with considerable reduction in required resources to implement the design as compared to Coregen and add/shift based design styles. Due to this reduction in required resources the proposed design can also be implemented on Spartan-3 FPGA device to provide cost effective solution for DSP and wireless communication applications.”
Highlights
Today’s consumer electronics such as cellular phones and other multimedia and wireless devices often require digital signal processing (DSP) algorithms for several crucial operations (Allred et al, 2004).Due to a growing demand for such complex DSP applications, high performance, low-cost Soc implementations of DSP algorithms are receiving increased attention among researchers and design engineers
In this paper, an important DSP function i.e. Finite impulse response (FIR) filter is implemented on Virtex-4 FPGA
It can be observed that the proposed PDA (PPDA) uses considerably less amount of resources on the target device as compared to other compared designs
Summary
Due to a growing demand for such complex DSP applications, high performance, low-cost Soc implementations of DSP algorithms are receiving increased attention among researchers and design engineers. In this paper, an important DSP function i.e. FIR filter is implemented on Virtex-4 FPGA. It uses look-up tables and accumulators instead of multipliers for computing inner products and has been widely used in many DSP applications such as DFT, DCT, convolution, and digital filters (White, 1989).
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