Modified Efficient Parallel Distributed Arithmetic based FIR Filter Architecture for ASIC and FPGA

Abstract

Digital FIR filters can be efficiently implemented using distributed arithmetic (DA). Original DA provides low throughput. Parallel DA is proven to be a promising technique for efficient DA implementation. Block-based parallel DA architecture proposed by Singhal and Mohanty is examined and improved by applying a modified LUT decomposition scheme. Experiments with different levels of LUT decomposition are performed with FIR filters of orders 16 and 32. The proposed architectures are implemented in Basys-3 (Artix-7, XC7A35T-1CPG236C) FPGA board. Several critical performance metrics such as the number of slices, maximum clock frequency, dynamic power consumption, and throughput are estimated for different filter orders for the targeted FPGA Board. The proposed architecture is also implemented for ASIC using a 45 nm NanGate open cell library and area, power, and delay are reported. Comparison with state-of-the-art DA architectures for FPGA implementation provides an average of 64% reduction in area and 22% improvement in throughput.