Dry Etching Research Articles

Vertical silicon nanowedge formation by repetitive dry and wet anisotropic etching combined with 3D self-aligned sidewall nanopatterning

Three-dimensional (3D) stacking of nano-devices is an effective method for increasing areal density, especially as downscaling of lateral device dimensions becomes impractical. This stacking is mainly achieved through plasma processing of stacked layers on top of a silicon (Si) substrate, which offers process flexibility but poses challenges in obtaining vertical sidewalls without plasma induced damage. A novel wafer-scale fabrication method is presented for realizing sub-200 nm vertically stacked Si nanowedges at the wafer scale, using iterative dry etching, wet anisotropic etching, and thermal oxidation. This approach forms nanowedges by the slow etching {111} Si planes, resulting in smooth surfaces at well-defined angles. A silicon nitride (Si3N4) hard mask is used in an iterative (etch-and-deposit) process, with its thickness determining the number of process iterations. By optimizing etch selectivity during dry etching and/or increasing the initial Si3N4 thickness, the number of process iterations can be increased. The periodicity of the nanowedges can be adjusted by varying the etch time of both dry and wet anisotropic etching. A thin silicon dioxide (SiO2) layer (∼6 nm) is grown on the nanowedges during each iteration. 3D sidewall patterning at the sub-20 nm scale is achieved using corner lithography and local oxidation of Si to selectively open the concave corners. Rhombus-shaped structures are formed at each concave corner after wet anisotropic etching of Si. This novel technology platform will allow for the 3D fabrication of high-density nanodevices for electronic, fluidic, plasmonic, and other applications.

Rapid Mg substitution to Ga-sites and slow defect recovery revealed by depth-resolved photoluminescence in Mg/N-ion-implanted GaN

Toward p-type GaN formation by Mg ion implantation (I/I) applicable to devices, depth-resolved photoluminescence (PL) revealed key behaviors during activation annealing for precise profile control, such as Mg substitution into Ga-sites (MgGa) and recovery of I/I defects. Depth profiles of the MgGa acceptor concentration were measured for Mg-I/I and Mg/N-I/I samples after ultra-high-pressure annealing at 1300 °C for 1–60 min. The cycle of low-damage dry etching and PL measurement was repeated over the I/I depth, and the MgGa concentration was estimated at each depth based on the calibration curve for the PL intensity ratio between acceptor-bound excitons (A0XA) and free excitons (FXA). In the region deeper than the I/I peak of 0.3 μm, almost all of the Mg atoms rapidly substituted into Ga-sites during the short annealing process. By contrast, the Mg substitution ratios in the shallower region were low when the annealing process was short but were improved by the sequential N-I/I. The low substitution ratio can be explained by MgGa bonding with nitrogen vacancy (VN)-related defects, while the implanted N-ions can compensate them. The PL intensity near the mean implantation depth of Mg/N-I/I was gradually improved as the annealing duration was increased to 60 min, indicating a slow reduction of nonradiative recombination centers. Simultaneously, the green luminescence associated with the VN-related defects decreased in intensity with increasing annealing time. Therefore, the main effect of prolonging annealing is the enhancement of slow defect recovery rather than enhancement of the Mg substitution as a fast process.

An efficient and noticeable wet etching method for PZT and its application in scanning mirrors

This study introduces an innovative wet etching method for magnetron sputtering lead zirconate titanate (PZT) thin films, leveraging a solution of HBF4 as the etchant and HCl for intermediate product removal. Compared to traditional dry etching techniques, the focus is on improving cost efficiency and etching performance. Wet etching offers numerous advantages, including lower costs, faster etching rates, minimal lateral etching, and smoother etch profiles, making it a viable alternative for fabricating MEMS piezoelectric devices. The effectiveness of this method was substantiated through the production and performance assessment of a 1D scanning mirror, demonstrating that the wet etched PZT retained its piezoelectric properties and was efficiently integrated into MEMS applications without adverse effects on its piezoelectric functionality. Results confirm that this wet etching approach not only maintains the structural integrity of PZT films but also supports the manufacturing of MEMS devices with precise dimensional control and reliable operational performance.

Aspect Ratio-Dependent Etching in Silicon using XeF2: Experimental Investigation and Comparative Analysis with Dry Etching Methods

Abstract Silicon machining plays a crucial role in shaping three-dimensional structures for Micro-Electro-Mechanical Systems (MEMS) applications. This study investigates Aspect Ratio Dependent Etching (ARDE) across various silicon etching processes, with a particular focus on Xenon Difluoride (XeF2) etching, in comparison to Reactive Ion Etching (RIE) and Deep Reactive Ion Etching (DRIE).By exploring different etching parameters, the study highlights the presence of ARDE in both plasma and non-plasma etching processes. Additionally, it is demonstrated that ARDE can be modeled by a saturating exponential function through experimental adjustment of parameters, enabling the prediction of etching profiles.

Interface properties study of black silicon solar cells with front surface a-Si:H/c-Si heterojunction

Abstract The exceptionally low reflectance of black silicon across a broad wavelength range makes it an intriguing surface texture for solar cell applications. Silicon heterojunction (SHJ) solar cells fabricated on black silicon (Si) formed by dry reactive ion etching (RIE) using inductive coupled plasma (ICP) on n-type Si are explored. The study is focused on the properties of the a-Si:H/c-Si interface, being a key issue for the photovoltaic performance of SHJ. Deep-level transient spectroscopy (DLTS) detected no radiation defect in Si after the etching. The surface of black Si was passivated with an intrinsic a-Si:H layer, followed by the deposition of p-type and n-type a-Si:H on the front and back sides, respectively. The SHJ solar cell photovoltaic performance based on black Si is strongly influenced by defect density at the a-Si:H/Si interface. Admittance spectroscopy and effective charge carrier lifetime measurements demonstrate that interface defect density decreases with the increase of (i)a-Si:H thickness. The value of 0.75 ms effective charge carrier lifetime was reached for single (i) a-Si:H layer passivation and 0.25 ms when (p)a-Si:H was deposited over the intrinsic a-Si:H layer. The measured open circuit voltage (VOC) values for the SHJ solar cells increase with the (i)a-Si:H layer thickness reaching 658 mV. However, the fill factor decreases with increasing (i) a-Si:H layer thickness, limiting the efficiency at the maximum value below 14% due to the thickness uniformity of the a-Si:H layer. The development of conformal growth of a-Si:H is a key issue for further improvement of black Si heterojunction solar cell photovoltaic performance. 

Fabricating 3D Si nanostructure via a novel Ga+ implantation enabled maskless dry etching process

Three-dimensional (3D) nanostructure is the key to the miniaturization of nonlinear photonic and electronic devices. Because of the great demand on the ultra-small nanostructures, the novel nanofabrication technologies with flexible 3D silicon (Si) fabrication capability are of great importance. Herein, by combining Ga+ FIB implantation and ICP dry etching processes, we proposed a novel Ga+ FIB implantation assisted maskless dry etching technology for direct fabrication of 3D Si nanostructures. We found that the implanted Ga+ induced amorphization layer in Si substrate acts as the ‘quasi-mask’ during the ICP dry etching process. The increase of Ga+ concentration in amorphization layer of Si substrate improves the etching resistance of the area. Moreover, enabled by high resolution and flexibility of FIB, the proposed technology is capable of directly fabricating various 3D Si nanostructures in a simple way, such as 3D nanoscale artificial bowtie arrays with sub-10 nm gaps, multi-scale 3D Si nanostructures with arbitrary patterns. More importantly, the proposed technology is compatible to current semiconductor manufacturing process. Benefiting by the advantages of simplicity and high efficiency, the proposed maskless dry etching process promises great application potential in the fields of nonlinear photonics and micro-electronics.

Towards atomic-scale smooth surface manufacturing of β-Ga2O3 via highly efficient atmospheric plasma etching

Abstract The highly efficient manufacturing of atomic-scale smooth β-Ga2O3 surface is fairly challenging because β-Ga2O3 is a typical difficult-to-machine material. In this study, a novel plasma dry etching method named plasma-based atom-selective etching (PASE) is proposed to achieve the highly efficient, atomic-scale, and damage-free polishing of β-Ga2O3. The plasma is excited through the inductive coupling principle and carbon tetrafluoride is utilized as the main reaction gas to etch β-Ga2O3. The core of PASE polishing of β-Ga2O3 is the remarkable lateral etching effect, which is ensured by both the intrinsic property of the surface and the extrinsic temperature condition. As revealed by density functional theory-based calculations, the intrinsic difference in the etching energy barrier of atoms at the step edge (2.36 eV) and in the terrace plane (4.37 eV) determines their difference in the etching rate, and their etching rate difference can be greatly enlarged by increasing the extrinsic temperature. The polishing of β-Ga2O3 based on the lateral etching effect is further verified in the etching experiments. The Sa roughness of β-Ga2O3 (001) substrate is decreased from 14.8 to 0.057 nm within 120 s, and the corresponding material removal rate reaches up to 20.96 μm/min. The polished β-Ga2O3 displays significantly improved crystalline quality and photoluminescence intensity, and the polishing effect of PASE is independent of the crystal faces of β-Ga2O3. In addition, the competition between chemical etching and physical reconstruction, which is determined by temperature and greatly affects the surface state of β-Ga2O3, is deeply studied for the first time. These findings not only demonstrate the high-efficiency and high-quality polishing of β-Ga2O3 via atmospheric plasma etching but also hold significant implications for guiding future plasma-based surface manufacturing of β-Ga2O3.

Comparative S/TEM study of superconducting Ta quantum resonators by wet and dry etching types

Superconducting resonators play a pivotal role in various quantum technology applications, such as quantum computing and high-frequency communication systems. The performance of these resonators is closely tied to the properties of the superconducting films used in their fabrication. In this study, we investigated the impact of wet and dry etching on tantalum (Ta) films leveraging advanced scanning transmission electron microscopy-based characterization methods and examined the morphological, chemical, and strain changes caused by the etching processes. Consequently, we report the significant differences between the two etching methods, with dry etching resulting in straight slanted sidewalls and a thinner oxidized layer, while wet etching produced curved sidewalls and undercuts. Both methods led to the formation of a residual Ta wedge at the lower part of the sidewall, causing lattice deformation, which could adversely influence the homogeneous operations of superconducting devices. These insights enhance our understanding of how etching influences superconducting films, offering valuable guidance for optimizing resonators and related devices. Our findings mark a significant stride in advancing quantum technologies and high-frequency communication by enhancing our practical understanding of superconducting material fabrication.

Neuronal activity in the ventral tegmental area during goal-directed navigation recorded by low-curvature microelectrode arrays

Navigating toward destinations with rewards is a common behavior among animals. The ventral tegmental area (VTA) has been shown to be responsible for reward coding and reward cue learning, and its response to other variables, such as kinematics, has also been increasingly studied. These findings suggest a potential relationship between animal navigation behavior and VTA activity. However, the deep location and small volume of the VTA pose significant challenges to the precision of electrode implantation, increasing the uncertainty of measurement results during animal navigation and thus limiting research on the role of the VTA in goal-directed navigation. To address this gap, we innovatively designed and fabricated low-curvature microelectrode arrays (MEAs) via a novel backside dry etching technique to release residual stress. Histological verification confirmed that low-curvature MEAs indeed improved electrode implantation precision. These low-curvature MEAs were subsequently implanted into the VTA of the rats to observe their electrophysiological activity in a freely chosen modified T-maze. The results of the behavioral experiments revealed that the rats could quickly learn the reward probability corresponding to the left and right paths and that VTA neurons were deeply involved in goal-directed navigation. Compared with those in no-reward trials, VTA neurons in reward trials presented a significantly greater firing rate and larger local field potential (LFP) amplitude during the reward-consuming period. Notably, we discovered place fields mapped by VTA neurons, which disappeared or were reconstructed with changes in the path–outcome relationship. These results provide new insights into the VTA and its role in goal-directed navigation. Our designed and fabricated low-curvature microelectrode arrays can serve as a new device for precise deep brain implantation in the future.

A Model for Dry Electron Beam Etching of Resist

This paper presents a detailed physical model for a novel method of two- and three-dimensional microstructure formation: dry electron beam etching of the resist (DEBER). This method is based on the electron-beam induced thermal depolymerization of positive resist, and its advantages include high throughput and relative simplicity compared to other microstructuring techniques. However, the exact mechanism of profile formation in DEBER has been unclear until now, hindering the optimization of this technique for certain applications. The developed model takes into account the major DEBER phenomena: e-beam scattering in resist and substrate, e-beam induced main-chain scissions of resist molecules, thermal depolymerization of resist, monomer diffusion, and resist reflow. Based on the developed model, a simulation algorithm was implemented, which allowed simulation of the profile obtained in resist by DEBER. Experimental verification of the DEBER model was carried out, which demonstrated the reliability of the model and its applicability for theoretical study of this method. The ultimate DEBER characteristics were estimated by simulation. The minimum line width and the maximum profile slope that could be obtained by DEBER were approximately 300 nm and 70°, respectively.

A Two-Step Dry Etching Model for Non-Uniform Etching Profile in Gate-All-Around Field-Effect Transistor Manufacturing.

The Gate-All-Around Field-Effect Transistor (GAAFET) is proposed as a successor to Fin Field-Effect Transistor (FinFET) technology to increase channel length and improve the device performance. The GAAFET features a complex multilayer structure, which complicates the manufacturing process. One of the most critical steps in GAAFET fabrication is the selective lateral etching of the SiGe layers, essential for forming the inner-spacer. Industry commonly encounters a non-uniform etching profile during this step. In this paper, a continuous two-step dry etching model is proposed to investigate the mechanism behind the formation of the non-uniform profiles. The model consists of four modules: anisotropic etching simulation, Ge atom diffusion simulation, Si/SiGe etch selectivity calculation and SiGe selective etching simulation. By calibrating and verifying this model with experimental data, the edge rounding and gradient etching rates along the sidewall surface are successfully simulated. Based on further examination of the influence of chamber pressure on the profile using this model, the inner-spacer shape is improved experimentally by appropriately reducing the chamber pressure. This work aims to provide valuable insights for etching process recipes in advanced GAAFETs manufacturing.

The Influence of Etching Method on the Occurrence of Defect Levels in III-V and II-VI Materials.

The influence of the etching method on the occurrence of defect levels in InAs/InAsSb type-II superlattice (T2SLs) and MCT photodiode is presented. For both analyzed detectors, the etching process was performed by two methods: wet chemical etching and dry etching using an ion beam (RIE-reactive ion etching). The deep-level transient spectroscopy (DLTS) method was used to determine the defect levels occurring in the analyzed structures. The obtained results indicate that the choice of etching method affects the occurrence of additional defect levels in the MCT material, but it has no significance for InAs/InAsSb T2SLs.

Process optimization of preparing CMOS backplane for ultrahigh pixel density red Micro-LED display

Abstract In this paper, an AlGaInP-based red Micro-LED display measured 17.78 mm (0.7 in), with a resolution of 1920 × 1080, a light-emitting mesa size of 6 μm, a pixel pitch of 8 μm and a pixel density of 3175 PPI was designed and fabricated with a CMOS driver backplane. The metal bump preparation technology of the complementary metal-oxide semiconductor driver backplane was optimized to enhance the bonding yield and create an optimal display effect. Improper sizing of the etched window in the SiO2 insulation and passivation layer can have a detrimental impact on the metal bump preparation and subsequent bonding process. By optimizing the settings of lithography and dry etching, the appropriate size of the etched aperture in the passivation layer was achieved. The high density, small size, and large aspect ratio of the photoresist openings for the bump fabrication made it challenging to remove the photoresist following the metal evaporation. To successfully remove the photoresist, it is important to carefully choose suitable experimental conditions for the removal. Afterwards, an 8 μm AlGaInP-based red Micro-LED display was effectively integrated with complementary metal-oxide semiconductor using flip-chip bonding technology. This work may be of reference value to those who work on ultrahigh density red Micro-LEDs that is challenging but crucial for future full color micro displays.

Process optimization of wet etching for split gate trench MOSFET

Abstract In this paper, the influence of etching technology on the performance of Split Gate Trench (SGT) MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor) is studied, and the significance and contribution of these improvements in the fields of mechatronics, robotics and control systems are discussed. Etching can be categorized into wet etching and dry etching, with wet etching being widely used for etching the gates of SGT MOSFETs. Due to the isotropic nature of wet etching, issues such as undercutting, trenching, and insufficient link-up region length can arise, leading to short circuits between the gate and the source. The improvement of this problem directly promotes the enhancement of mechatronics system efficiency, the improvement of robot dynamic performance and accuracy, and the realization of efficient control strategies in control systems. By optimizing the process flow to enhance the adhesion of photoresist, increase the density of the HDP (High Density Plasma) deposited oxide film, and adjust the etching rate and frequency of wet etching, it is possible to mitigate the issues of isotropy and insufficient precision in wet etching. These improvements address failure phenomena and enhance product yield.

Highly Photoresponsive Vertically Stacked Silicon Nanowire Photodetector with Biphasic Current Stimulator IC for Retinal Prostheses

This paper presents an integrated approach for a retinal prosthesis that overcomes the scalability challenges and limitations of conventional systems that use external cameras. Silicon nanowires (SiNWs) are utilized as photonic sensors due to their nanoscale dimensions and high surface-to-volume ratio. To enhance these properties and achieve high photoresponsivity, our research team developed a vertically stacked SiNW structure using a fabrication method entirely based on dry etching. The fabricated SiNW photodetector demonstrated excellent electrical and optical characteristics, including linear I–V characteristics that confirmed ohmic contact formation and high photoresponsivity exceeding 105 A/W across the 400–800 nm wavelength range. The SiNW photodetector, following its integration with a switched capacitor stimulator circuit, exhibited a proportional increase in stimulation current in response to higher light intensity and increased SiNW density. In vitro experiments confirmed the efficacy of the integrated system in inducing neural responses from retinal cells, as indicated by an increased number of neural spikes observed at higher light intensities and SiNW densities. This study contributes to sensor technology by demonstrating an approach to integrating nanostructures and electronic components, which enhances control and functionality.

Thermally tunable microring resonators based on germanium-on-insulator for mid-infrared spectrometer

We present a thermally tunable microring resonator (MRR) implemented on a Ge-on-insulator (Ge-OI) photonic platform tailored for mid-infrared spectrometer applications. Thanks to the favorable thermo-optic effect of Ge, we characterized the optical and thermal properties of the thermally tunable Ge-OI MRR through rigorous optical and thermal numerical analyses. Building upon the simulation, a ring-shaped Au heater was successfully integrated into the Ge-OI MRR that was fabricated by using a direct wafer bonding process, followed by electron-beam lithography and dry etching techniques. Observations via thermo-reflectance microscopy revealed the temperature change within the Ge induced by heat transfer from the applied bias to the Au heater. Notably, the measured temperature change of 17 K at an applied electrical power of 181.7 mW closely aligned with the simulated values. In optical measurement, the heater-integrated Ge-OI MRR exhibited the tunability of 33.7 nm/W (0.36 nm/K) and the loaded Q factor of 21k at 4.2 µm wavelength with no bias. Hence, our demonstration of the Ge-OI tunable ring filter for mid-IR spectrometers could be a promising technology employing photonic integrated circuits for diverse applications in optical communication and spectral sensing.

Nonhalogen Dry Etching of Metal Carbide TiAlC by Low-Pressure N2/H2 Plasma at Room Temperature.

Ternary metal carbide TiAlC has been proposed as a metal gate material in logic semiconductor devices. It is a hard-to-etch material due to the low volatility of the etch byproducts. Here, a simple, highly controllable, and dry etching method for TiAlC has been first presented using nonhalogen N2/H2 plasmas at low pressure (several Pa) and 20 °C. A capacitively coupled plasma etcher was used to generate N2/H2 plasmas containing active species, such as N, NH, and H to modify the metal carbide surface. The etch rate of TiAlC was obtained at 3 nm/min by using the N2/H2 plasma, whereas no etching occurred with pure N2 plasma or pure H2 plasma under the same conditions. The surface roughness of the TiAlC film etched by N2/H2 plasma was controlled at the atomic level. A smooth etched surface was achieved with a root-mean-square roughness of 0.40 nm, comparable to the initial roughness of 0.44 nm. The plasma properties of the N2/H2 plasmas were diagnosed by using a high-resolution optical emission spectrometer, detecting the NH molecular line at 336 nm. The etching behavior and plasma-surface reaction between N2/H2 plasma and TiAlC were investigated by using in situ spectroscopic ellipsometry, in situ attenuated total reflectance-Fourier transform infrared spectrometry, and X-ray photoelectron spectroscopy. The findings indicate that the N-H, C-N, and Ti(Al)-N bonds form on the TiAlC surface etched by the N2/H2 plasmas. The mechanism for etching of TiAlC involving transformation reactions between inorganic materials (metal carbides) and inorganic etchants (N2/H2 plasma) to form volatile organic compounds such as methylated, methyl-aminated, and aminated metals is proposed. Nonhalogen or nonorganic compound etchants were used during the etching process. The study provides useful insights into microfabrication for large-scale integrated circuits.

Microfabricated vapor cells with chemical polishing and two-step low-temperature anodic bonding for single-beam magnetometer

With the miniaturization of quantum sensors, the fabrication of alkali metal vapor cells based on micro-electromechanical systems (MEMS) has become increasingly important. However, the fabrication of MEMS vapor cells remains a challenge. In this study, a microfabricated millimeter-level vapor cell was fabricated and tested. The silicon cavity was fabricated by dry etching and chemical polishing. After injection of alkali metal and buffer gas, a two-step low-temperature anodic bonding was employed. The first step was non-isothermal to keep the alkali metal in the low-temperature pole plate and the second step was isothermal to improve the bonding strength, enhancing the hermeticity. Then, the vapor cell was tested for sidewall roughness, bonding strength, and leakage rate. Subsequently, Rb D1 line absorption spectroscopy, stability, and the single-beam magnetometer signal were tested. The results show the fabricated vapor cell had high stability, providing a basis for the miniaturization of quantum devices.

High-density integration of uniform sub-22 nm silicon nanowires for transparent thin film transistors on glass

Ultrathin catalytical silicon nanowires (SiNWs), grown as orderly arrays upon glass substrates, are ideal 1D channels for the construction of high-performance field effect transistors for low-power and high aperture/transparency electronics. In this work, a rather uniform growth integration of high-density ultrathin SiNWs has been accomplished directly on glass substrate at 290 °C, via an in-plane solid–liquid-solid mechanism. The indium (In) catalyst thickness deposited on the dense guiding terrace steps was identified as a key parameter to suppress the size dispersion of the In droplets, and thus enable a uniform growth of ultrathin SiNWs with diameters down to DNW=21.8 ± 1.8 nm, a close-to-unity guided growth rate and an excellent transparency > 90 % in spectrum ranging from 350 nm to 950 nm. Based on a convenient dry plasma etching and low-temperature passivation procedure, high-performance SiNW transistors have been successfully fabricated upon a dense array of parallel SiNWs as channels with a narrow NW-to-NW spacing of 100 nm. A high current ratio Ion/Ioff > 107, a low off-state current down to 0.1 pA, a steep subthreshold swing of SS∼120 mV dec-1 and excellent positive and negative bias stabilities have been demonstrated, as well as SiNW-based inverter logics that achieve a gain of 14.6 V/V under a drive voltage of 2.25 V. These results highlight the potential of catalytic SiNWs to serve as advantageous 1D channels for large-area display or transparent electronics.

Efficient access to non-damaging GaN (0001) by inductively coupled plasma etching and chemical–mechanical polishing

As third-generation semiconductors advance, gallium nitride (GaN)-based devices are gaining significant attention. However, the processing of GaN substrates directly affects device performance. This paper proposes an ICP etching-chemical–mechanical polishing (CMP) strategy to efficiently produce GaN single-crystal substrates with non-destructive, atomic-level surfaces. The process time is significantly reduced from 15 h to 1.5 h. The wet oxidation reaction during CMP eliminates impurities and defects from dry etching. FIB-STEM tests confirm that this method is non-destructive, as the ICP technique enables isotropic etching, and CMP introduces no new damage to the substrate. This approach enhances the productivity of large-size GaN single-crystal substrates, promoting their broader application in laser displays, RF devices, and power electronics.